Patents by Inventor Chun-Wei Chang

Chun-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265757
    Abstract: A floating connector includes a shell, a plurality of electrodes, two buckle members and a floating member. The shell has an accommodating space and a plurality of openings. The electrodes are disposed in the accommodating space and penetrate the openings to protrude from the openings. The buckle members are respectively disposed on two sides of the accommodating space. Each of the buckle members includes a fixed part, a contacting part, and an elastic part. The floating member includes a body, a plurality of electrode notches, and a bump. The electrode notches are formed on one side of the body that near the electrodes for receiving the electrodes protruding from the openings. The bump is disposed on the body and correspondingly to the notch, and the width of the bump is not greater than that of the notch, so that the bump is restricted in the notches by the guiding structure.
    Type: Application
    Filed: July 9, 2020
    Publication date: August 26, 2021
    Inventors: Hsien-Chang Lin, Chun-Wei Chang
  • Patent number: 11086221
    Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
  • Patent number: 11077531
    Abstract: A fixture block composite structure for workpiece positioning comprises a fixture block group composed of at least a stop fixture block and at least a one-sided movable fixture block. The stop fixture block is fixed to a base by a plurality of mountings, and two opposite lateral sides of the stop fixture block in the extending direction of base are provided with a fixed upright positioning plane respectively. The one-sided movable fixture block has a fixed holder, the holder is fixed to the base by a plurality of mountings. The holder is provided with a movable piece which can be driven to reciprocate towards the positioning plane on the stop fixture block. The movable piece is provided with a clamping surface on one side facing the positioning plane.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 3, 2021
    Inventor: Chun-Wei Chang
  • Publication number: 20210226012
    Abstract: A method of making a semiconductor device includes defining a first fin structure over a major surface of a substrate, wherein the first fin includes a first material. The method includes defining a second fin structure over the major surface of the substrate. Defining the second fin structure includes forming a lower portion of the second fin structure, closest to the substrate, having the first material, and forming an upper portion of the second fin structure, farthest from the substrate, having a second material different from the first material. The method includes forming a dielectric material over the substrate and between the first and second fin structures. The method includes removing the upper portion of the second fin structure, wherein removing the upper portion of the second fin structure includes reducing a height of the second fin structure to be less than a height of the first fin structure.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 22, 2021
    Inventors: Jhong-Sheng WANG, Jiaw-Ren SHIH, Chun-Wei CHANG, Sheng-Feng LIU
  • Publication number: 20210193705
    Abstract: A method includes forming a first photoresist layer on a front side of a device substrate and having first trenches spaced apart from each other. A first implantation process is performed using the first photoresist layer as a mask to form first isolation regions in the device substrate. A second photoresist layer is formed on the front side and has second trenches. A second implantation process is performed using the second photoresist layer as a mask to form second isolation regions in the device substrate and crossing over the first isolation regions. A third photoresist layer is formed on the front side and has third trenches spaced apart from each other. A third implantation process is performed using the third photoresist layer as a mask to form third isolation regions in the device substrate and crossing over the first isolation regions but spaced apart from the second isolation regions.
    Type: Application
    Filed: March 13, 2020
    Publication date: June 24, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao CHIU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Patent number: 11004880
    Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 10978440
    Abstract: A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shou-En Liu, Chun-Wei Chang, Bi-Ling Lin, Yung-Sheng Tsai, Jiaw-Ren Shih
  • Publication number: 20210097227
    Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Hsien YU TSENG, Chun-Wei CHANG, Szu-Lin LIU, Amit KUNDU, Sheng-Feng LIU
  • Patent number: 10930701
    Abstract: A light-emitting device includes a first semiconductor layer having an uppermost surface and a bottommost surface; a first light-emitting structure and a second light-emitting structure formed on the same first semiconductor layer, wherein the first semiconductor layer is continuous; a first trench formed between the first and the second light-emitting structures; and a second electrode formed on the second semiconductor layer and including a second pad and a plurality of second extending parts extending from the second pad; wherein the second pad is between the first and the second light-emitting structures, and the plurality of second extending parts extends to the first and the second light-emitting structures, respectively; wherein the first trench passes through the uppermost surface but does not extend to the bottommost surface; wherein the first trench includes an equal width in a top view.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 23, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chen Ou, Chun-Wei Chang, Chih-Wei Wu, Sheng-Chih Wang, Hsin-Mei Tsai, Chia-Chen Tsai, Chuan-Cheng Chang
  • Patent number: 10919128
    Abstract: A modular side-by-side vise structure including a base, a fixture block group located on the base, and a side clamping piece group; the side clamping piece has an upper part and a lower part, and a bolt is screwed in the upper part to prop the lower part, so that the stopper and movable fixture block cling to the base tightly; or the side grooves on both sides of the stopper and movable fixture block are provided with bolt holes, and the inner wall of side clamping piece is provided with a punch hole, the bolt is screwed in the bolt hole through the punch hole, so that the stopper and movable fixture block cling to the base tightly. Therefore, it is unnecessary to hold up the side clamping piece with a hand while tightening or loosening the bolt, favorable for the technician to implement quick assembly or disassembly.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 16, 2021
    Inventor: Chun-Wei Chang
  • Publication number: 20210027732
    Abstract: The present disclosure provides a source driver module for driving a display panel. The source drive module includes a source driver circuit, a first conductive wire and a first switch unit. The first conductive wire is electrically connected to the source driver circuit. The first switch unit is connected between the first conductive wire and a first data line of the display panel to conduct current therebetween during a first data outputting period and a second data outputting period, and to interrupt current therebetween during a first switch-off period connecting the first data outputting period and the second data outputting period. The source driver circuit outputs a first voltage signal during the first data outputting period and the first switch-off period; it outputs a second voltage signal during the second data outputting period; and it outputs the first voltage signal during the first switch-off period.
    Type: Application
    Filed: May 20, 2020
    Publication date: January 28, 2021
    Inventors: JIE-CHUAN HUANG, CHUN-WEI CHANG, CHIA-MING WU
  • Publication number: 20210005649
    Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
    Type: Application
    Filed: September 16, 2020
    Publication date: January 7, 2021
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 10867109
    Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien Yu Tseng, Chun-Wei Chang, Szu-Lin Liu, Amit Kundu, Sheng-Feng Liu
  • Publication number: 20200365645
    Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
  • Publication number: 20200350715
    Abstract: The present invention discloses a buckle connector connecting a main board and a sub-board. The buckle connector includes a first connecting portion and a second connecting portion. The first connecting portion mainly provides a first coupling member and the second connecting portion mainly provides a second coupling member. The first connecting portion and the second connecting portion are disposed on the same plane by coupling the first coupling member and the second coupling member when the first connecting portion moves to the second connecting portion in one direction.
    Type: Application
    Filed: April 9, 2020
    Publication date: November 5, 2020
    Inventors: Shien-Chang LIN, Chun-Wei CHANG
  • Publication number: 20200327836
    Abstract: A display panel includes multiple data lines, a scan lines, pixel circuit and a driving circuit. The data lines are configured to receive multiple data signals in a display period. There is a buffer period before the display period. The scan line is configured to receive a scan signal during the display period. The pixel circuit is electrically connected to the data lines and the scan line for receiving the data signals and the scan signal. The driving circuit is electrically connected to the data line, and configured to receive multiple charging signals during the buffer period. The charging signals are corresponding to the data lines and gradually increase so that the driving circuit charges the data lines according to the charging signals.
    Type: Application
    Filed: March 4, 2020
    Publication date: October 15, 2020
    Inventors: Chun-Wei CHANG, Jie-Chuan HUANG
  • Patent number: 10797156
    Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10797091
    Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 10782814
    Abstract: A touch display panel includes a pixel array, a touch module, and a multiplexer circuit. The pixel array includes a plurality of pixels, a plurality of gate lines, and a plurality of source lines. The pixels are electrically coupled to the source lines and the gate lines. The touch module and the pixel array are overlapped. The multiplexer circuit is coupled between all of the source lines and a source driver and has a plurality of multiplexers. The multiplexers are respectively coupled to n source lines and respectively include a plurality of switches and a bypass trace. The switches are respectively coupled between the first source line to the (n?1)th source line of the n source lines and the source drivers. The bypass trace is coupled between the nth source line of the n source lines and the source driver.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Au Optronics Corporation
    Inventors: Rong-Fu Lin, Chun-Wei Chang, Shu-Hao Huang, Sung-Yu Su, Jie-Chuan Huang, Yun-I Liu
  • Patent number: 10734436
    Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng