Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract: A cooling structure integrated all-in-one computer includes a display device including a hollow frame having retaining members located therein, a first electric connector mounted in the hollow frame and a display module mounted in the hollow frame, and a mainframe including an aluminum extruded casing slidably inserted into a back opening of the hollow frame, engaging members located in the casing for engaging the retaining members upon insertion of the casing into the hollow frame, and a motherboard mounted in a recessed accommodation chamber in the casing with heat-emitting sources thereof abutted against respective heat-transferring bearing blocks of the casing for quick dissipation of heat and a second electric connector thereof connected to the first electric connector.

Abstract: An electronic device and hinge assembly includes an electronic device body including a base and a main unit, and hinge devices pivotally connecting the base and the main unit for allowing adjustment of the angular position of the main unit relative to the base step by step in a series of angles. Each hinge device includes a casing affixed to one of the base and the main unit, a pivot shaft connected to the base and the main unit and rotatably inserted through the casing and secured by a retaining ring, and a friction wheel set and a damper mounted on the pivot shaft. The friction wheel set includes a first friction wheel and having recessed portions equiangularly spaced at one side thereof, and a second friction wheel rotatable with the pivot shaft relative to the first friction wheel and having raised portions respectively engageable into the recessed portions.

Abstract: A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.

Abstract: An electronic device and hinge assembly includes an electronic device body including a base and a main unit, and hinge devices pivotally connecting the base and the main unit for allowing adjustment of the angular position of the main unit relative to the base step by step in a series of angles. Each hinge device includes a casing affixed to one of the base and the main unit, a pivot shaft connected to the base and the main unit and rotatably inserted through the casing and secured by a retaining ring, and a friction wheel set and a damper mounted on the pivot shaft. The friction wheel set includes a first friction wheel and having recessed portions equiangularly spaced at one side thereof, and a second friction wheel rotatable with the pivot shaft relative to the first friction wheel and having raised portions respectively engageable into the recessed portions.

Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer over a substrate; and a first gate feature in the ILD layer, the first gate feature comprising a first gate material and having a first resistance, wherein the first gate material comprises a first conductive material. The semiconductor device further includes a second gate feature in the ILD layer, the second gate feature comprising a second gate material and having a second resistance higher than the first resistance, wherein the second material comprises at least 50% by volume silicon oxide.

Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.

Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.

Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

Abstract: A charge pump circuit includes a plurality of branches coupled in parallel, each branch including a plurality of sub-blocks coupled in series, and each sub-block including a unit pump circuit. The charge pump circuit also includes a plurality of clock transfer circuits coupled to corresponding ones of the plurality of branches for providing clock signals to the corresponding branches. The sub-blocks of different branches are enabled and driven by the clock signals at different times.

Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.

Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.

Abstract: In a method for adjusting brightness of a display screen of an electronic device, a current brightness value of the display screen and a current illumination value of ambient lights are acquired, and then are processed by denoising and normalizing. The current brightness value is adjusted to meet user preferences by self-learning according to the current illumination value and a brightness/illumination relationship table which stores a relationship between brightness values of the display screen and illumination values of ambient lights determined according to the user preferences.

Abstract: The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.

Abstract: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.

Abstract: The present disclosure provides a semiconductor structure includes a gate structure disposed over a substrate, wherein the gate structure includes a high-k dielectric layer and a work function structure. The high-k dielectric layer includes a base portion and a side portion, the side portion is extended from an end of the base portion, the side portion is substantially orthogonal to the base portion. The work function structure includes a first metal disposed over the high-k dielectric layer and a second metal disposed over the first metal and including a bottom portion and a sidewall portion extended from an end of the bottom portion, wherein the first metal includes different materials from the second metal, and a length of an interface between the sidewall portion and the bottom portion to a length of the bottom portion within the high-k dielectric layer is in a predetermined ratio.

Abstract: The present disclosure provides a semiconductor structure includes a gate structure disposed over a substrate, wherein the gate structure includes a high-k dielectric layer and a work function structure. The high-k dielectric layer includes a base portion and a side portion, the side portion is extended from an end of the base portion, the side portion is substantially orthogonal to the base portion. The work function structure includes a first metal disposed over the high-k dielectric layer and a second metal disposed over the first metal and including a bottom portion and a sidewall portion extended from an end of the bottom portion, wherein the first metal includes different materials from the second metal, and a length of an interface between the sidewall portion and the bottom portion to a length of the bottom portion within the high-k dielectric layer is in a predetermined ratio.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.