Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A bandgap reference circuit includes a first bipolar junction transistor (BJT) in series with a first current generator, the first BJT and the first current generator configured to produce a first proportional to absolute temperature (PTAT) signal. The circuit also includes a second BJT in series with a second current generator, the second BJT and the second current generator configured to produce a second PTAT signal. The bandgap reference circuit maintains a current through at least one of the first BJT or the second BJT within a constant ideality factor region of the at least one of the first BJT or the second BJT.

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.

Abstract: A hotkey triggering system for an electronic device includes a first key determination unit, a first key time determination, a second key determination unit and a hotkey processing unit. The first key determination unit is configured to determine whether a first key being pressed is a hotkey selection key. The first key time determination unit is configured to determine whether the first key is pressed for a sufficient period of time when the first key is determined to be the hotkey selection key. The second key determination unit is configured to determine whether a second key being pressed is a hotkey when the first key is determined to be pressed for the sufficient period of time. The hotkey processing unit is configured to execute a hotkey function when the second key is determined to be the hotkey, and the hotkey function includes varying hardware state of the electronic device.

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A method for detecting and warning about a human or animal left in a vehicle by a user includes detecting whether the vehicle is in a first condition of engine off and in a second condition of being locked. An image obtaining device is controlled to capture images of interior of the vehicle when the vehicle meets the first and second conditions. Presence of a human or animal is detected by analyzing the images of the current environment inside the vehicle. A preset prompt is transmitted when a human or animal is detected.

Abstract: A method of forming a semiconductor device includes implanting dopants in a first region of the semiconductor device to form a source region. The method further includes forming a guard ring in a second region of the semiconductor device, the guard ring being separated from the source region by a first spacing. The method further includes depositing a first heat conductive layer over the source region, wherein the first heat conductive layer is directly coupled to the source region and directly coupled to the guard ring. The first heat conductive layer is configured to dissipate heat generated by the semiconductor device from the source region to the guard ring.

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.

Abstract: A hotkey triggering system for an electronic device includes a first key determination unit, a first key time determination, a second key determination unit and a hotkey processing unit. The first key determination unit is configured to determine whether a first key being pressed is a hotkey selection key. The first key time determination unit is configured to determine whether the first key is pressed for a sufficient period of time when the first key is determined to be the hotkey selection key. The second key determination unit is configured to determine whether a second key being pressed is a hotkey when the first key is determined to be pressed for the sufficient period of time. The hotkey processing unit is configured to execute a hotkey function when the second key is determined to be the hotkey, and the hotkey function includes varying hardware state of the electronic device.

Abstract: A system for updating a sign-on logo of an electronic device includes an initialization unit, an image file determination unit, an image selection determination unit, and a logo display unit. The initialization unit is configured to initialize a hardware of the electronic device. The image file determination unit is configured to determine whether a system storage module of the electronic device stores a plurality of image files after the hardware is initialized. The image selection determination unit is configured to determine whether one of the image files is selected when the system storage module is determined storing the image files. The logo display unit is configured to display a logo image when the one of the images files is determined being selected, wherein the logo image corresponds to the one of the images files.

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first top OD region, a first bottom OD region, and a first nanowire. A second GAA transistor includes: a second top OD region, a second bottom OD region, and a second nanowire. The first top OD region, the first bottom OD region, and the first nanowire are symmetrical with the second top OD region, the second bottom OD region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow from the first top OD region to the first bottom OD region, and the second GAA transistor is arranged to provide a second current to flow from the second top OD region to the second bottom OD region.

Abstract: A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces and fabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The arranging is based on at least a length of a signal trace of the plurality of signal traces.