Abstract: Disclosed is a display panel including a first emitting part and a second emitting part spaced apart from each other. Each of the first and second emitting parts includes an separator and at least one emitting part. The separator includes a first isolation portion. The first isolation portion includes first portions spaced apart from each other and second portions, each of the second portions is bent from each of the first portions and is disposed between adjacent ones of the first portions.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

Abstract: A display panel includes a transistor, a light emitting device electrically connected to the transistor, a connection wiring electrically connecting the transistor to the light emitting device and including side surfaces, a capping pattern disposed on the transistor and contacting at least a side surface among side surfaces, an upper insulating layer disposed on the transistor and including a first opening that overlaps the at least the side surface, and a pixel definition layer disposed on the upper insulating layer and covering the first opening of the upper insulating layer.

Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Abstract: A cosmetic container having a wiper capable of removing a cosmetic liquid from an application support rod having a non-circular cross-sectional area is proposed. The cosmetic container includes a container (110) in which the cosmetic liquid is accommodated, a container cap (120) opened/closed with respect to an injection port (112) of the container (110), and an application part (130) rotatably fitted and coupled to the container cap. The wiper (140) is coupled to an inner side of the injection port (112) of the container, a through-hole (144) of the cleaner part (142) is formed in a circular shape, the application part includes an application support rod (132) and an application member (134), an airtight recessed groove (133) is formed on an upper portion of the application support rod, and the application support rod extended from a lower portion of the airtight recessed groove has a non-circular cross-sectional area.

Abstract: Integrated circuit packages and methods of forming the same are provided. In an embodiment, a device includes: a power distribution interposer including: a first bonding layer; a first die connector in the first bonding layer; and a back-side interconnect structure including a power rail connected to the first die connector; and an integrated circuit die including: a second bonding layer directly bonded to the first bonding layer by dielectric-to-dielectric bonds; a second die connector in the second bonding layer, the second die connector directly bonded to the first die connector by metal-to-metal bonds; and a device layer on the second bonding layer, the device layer including a contact and a transistor, the transistor including a first source/drain region, the contact connecting a back-side of the first source/drain region to the second die connector.

Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.

Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.

Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.

Abstract: A light-transmitting antenna includes a substrate, a first conductive pattern, and a second conductive pattern. The first conductive pattern has a first feeder unit, a first radiation unit, a second radiation unit, and a first connection unit. The first feeder unit and the first connection unit are connected to two sides of the first radiation unit. The first connection unit connects the first radiation unit and the second radiation unit. The second conductive pattern has a second feeder unit, a third radiation unit, a fourth radiation unit, and a second connection unit. The second feeder unit and the second connection unit are connected to two sides of the third radiation unit. The second connection unit connects the third radiation unit and the fourth radiation unit. An orthogonal projection of the second feeder unit on a first surface of the substrate at least partially overlaps the first feeder unit.

Abstract: A method for recovering ashing rate in a plasma processing chamber includes positioning a substrate in a processing volume of a processing chamber, wherein the substrate has a silicon chloride residue formed thereon. The method further includes evaporating the silicon chloride residue from the substrate. The method further includes depositing the evaporated silicon chloride on one or more interior surfaces in the processing volume. The method further includes exposing the deposited silicon chloride to an oxidizing environment to convert the deposited silicon chloride to a silicon oxide passivation layer. The oxidizing environment can comprise an oxygen-containing plasma, oxygen radicals, or a combination thereof.

Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer, and having holes; a first insulation layer disposed on the semiconductor epitaxial structure and having first and second grooves; a first pad electrically connected to the first semiconductor layer through the first grooves; and a second pad electrically connected to the second semiconductor layer through the second grooves. A projection of the first pad does not overlap projections of the holes. A projection of the second pad does not overlap the projections of the holes. The first pad includes a first pad connection portion and first pad extension portions; the second pad includes a second pad connection portion and second pad extension portions. Projections of the second grooves fall between projections of the first and second pad extension portions. Two other aspects of the light-emitting device are also provided.

Abstract: A display device includes a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines, a data driver which outputs data signals to the plurality of data lines including a first data line and a second data line branched from a data output terminal connected to the data driver, and a scan driver which outputs scan signals to the plurality of scan lines. A first scan output terminal and a second scan output terminal respectively connected to the plurality of scan lines are connected to the scan driver. One of the first scan output terminal and the second scan output terminal is connected to a resistance.

Abstract: A method for handling a multi-cell scheduling and a user equipment is provided. In the method, downlink control information (DCI) from a first serving cell is received. A first number of multiple scheduled cells according to the DCI is determined. The DCI is configured to schedule at least one communication on the scheduled cells. Th communication is performed on at least one of the first number of the scheduled cells according to the DCI. The DCI includes at least one single DCI field, at least one separate DCI field and at least one configurable DCI field.

Abstract: Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe including a die pad, a first ridge formed at a first outer edge of the die pad, a second ridge formed at a second outer edge of the die pad opposite of the first outer edge and separate from the first ridge, and a plurality of leads surrounding the die pad. A semiconductor die is attached to the die pad by way of a die attach material. The semiconductor die is located on the die pad between the first ridge and the second ridge. An encapsulant encapsulates the semiconductor die and at least a portion of the package leadframe.