Abstract: A UE for beam failure detection is provided. The UE includes a radio frequency (RF) signal processing device. The RF signal processing device receives a first candidate-beam reference-signal (RS) list and a second candidate-beam RS list and reports a beam failure information. The first candidate-beam RS list is associated with a first beam-failure-detection RS (BFD-RS) set and the second candidate-beam RS list is associated with a second BFD-RS set. The beam failure information includes at least one of following: at least on component carrier (CC) index, at least one new candidate beam, an identity of BFD-RS set, or an CORESETPoolIndex.

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

Abstract: The present application relates to a hybrid cord including a bio-based nylon primarily twisted yarn. According to the present application, while including a primarily twisted yarn including bio-based nylon having a higher modulus compared to chemical-based nylon, there is provided a hybrid cord and has elongation and fatigue resistance equivalent to or higher than commercially required levels (i.e., the level that the cord including a conventional chemical-based nylon primarily twisted yarn has).

Abstract: Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.

Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.

Abstract: A multilayer ceramic capacitor includes a ceramic body having a dielectric layer, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion arranged on end portions of the internal electrodes exposed through respective opposing surfaces of the ceramic body. The ceramic body includes an active portion having the plurality of internal electrodes arranged to overlap each other with the dielectric layer interposed therebetween to form capacitance, and cover portions disposed above an uppermost and below a lowermost internal electrode of the active portion. The first and second side margin portions include tin (Sn), and a content of Sn included in the first and second side margin portions is greater than a content of Sn included in the dielectric layer of the active portion.

Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion respectively arranged on end portions of the internal electrodes exposed to first and second surfaces. The first and second side margin portions each include a first region adjacent to an outward facing side surface of the respective side margin portion, and a second region adjacent to the internal electrodes exposed to the first and second surfaces of the ceramic body, and an average size of dielectric grains included in the second region is larger than an average size of dielectric grains included in the first region.

Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Abstract: An optical fingerprint sensing module includes an image sensing device, a light source and a light shielding structure. The image sensing device is configured to sense light transmitted from a fingerprint of a finger on a display panel. The image sensing device includes a light sensing plane having a first geometric center. The light source includes a light emitting plane having a second geometric center. The first geometric center is separated from the second geometric center by a distance from 2 mm to 20 mm. The light shielding structure is disposed between the image sensing device and the light source. In examples, the optical fingerprint sensing module further includes a field angle controller to constrain light pass there through with a field angle of 5-60 degrees. A display device including an optical fingerprint sensing module is disclosed herein as well.

Abstract: Systems and methods for switching between a power supply mode and an electronic load mode are disclosed. For switching from the power supply mode to the electronic load mode, the method comprises the steps of: deactivating a power element; activating a current control module and a phase-locked loop to obtain a voltage phase of a device under test; calculating a turn-on amount of the power element according to a current setting value and the voltage phase; and causing the power element to generate a load current for the device under test. For switching from the electronic load mode to the power supply mode, the method comprises the steps of: deactivating the power element; activating a voltage control module; calculating the turn-on amount of the power element according to a voltage setting value; and causing the power element to input a corresponding voltage to the device under test.

Abstract: A semiconductor structure having a silver-indium transient liquid phase bonding joint is provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.

Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.

Abstract: A clip for securing one or more cables associated with a computing device includes a baseplate, a first wall, and a second wall. The first wall and the second wall extend from the baseplate. The first wall has a first inward projection at a distal end thereof. The second wall has a second inward projection at a distal end thereof. The first wall is generally parallel to the second wall. The first wall and the second wall are spaced apart from each other by an interior space configured to receive the one or more cables. The first inward projection and the second inward projection aid in preventing the one or more cables from moving outside of the interior space.

Abstract: The present disclosure relates to a display panel and an electronic device. The display panel includes a driving array; first light-emitting deices electrically connected with the driving array; and second light-emitting devices located between at least two of the first light-emitting devices and electrically connected with the driving array. In a case where the first light-emitting devices are in a working state and the second light-emitting devices are in a first state, the display panel is in a first mode; and in a case where the first light-emitting devices are in a working state and the second light-emitting devices are in a second state, the display panel is in a second mode, wherein a visual angle of the display panel in the first mode is greater than 0 and smaller than a visual angle of the display panel in the second mode.

Abstract: In an embodiment, a photoinitiation apparatus includes: a set of illumination sources or elements configured for outputting optical energy; a body structure having a proximal body structure portion confining a proximal volume of explosive medium, an intermediate body structure portion confining an intermediate volume of explosive medium, and a distal body structure portion confining a distal volume of explosive medium, wherein the proximal volume of explosive medium is optically coupled to portions of the first volume of explosive medium, at least one of the proximal volume of explosive medium and the distal volume of explosive medium is a tertiary explosive medium, and (a) the body structure does not carry a primary explosive composition and does not carry a secondary explosive composition, and/or (b) each of the proximal, intermediate, and distal volumes of explosive media has an initiation sensitivity that is less than cyclotrimethylenetrinitramine (RDX) based explosive compositions.

Abstract: Provided is an overlay mark including a first pattern and a second pattern. The first pattern includes a plurality of first strip shapes and a plurality of first dot shapes. The plurality of first strip shapes extend along a first direction and are arranged in parallel along a second direction. The plurality of first dot shapes are respectively disposed between the plurality of first strip shapes. The second pattern includes a plurality of second strip shapes and a plurality of second dot shapes. The plurality of second strip shapes extend along the second direction and are arranged in parallel along the first direction. The plurality of second dot shapes are respectively disposed between the plurality of second strip shapes.

Abstract: A benzoxazine resin and a method for manufacturing the same, and a resin composition are provided. The benzoxazine resin is obtained from a condensation polymerization reaction of a phenolic compound, formaldehyde, and a primary amine compound that are used as a reactant. The phenolic compound includes a dicyclopentadiene phenol resin and bisphenol A. The primary amine compound includes 2,6-dimethylaniline and m-xylylenediamine. The resin composition includes the benzoxazine resin, an epoxy resin, and a bismaleimide resin. Based on a total weight of the benzoxazine resin, the epoxy resin, and the bismaleimide resin being 100 phr, an amount of the benzoxazine resin ranges from 30 phr to 50 phr.

Abstract: The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N?1. The data state N?1 has a lower voltage threshold than the data state N.