Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Abstract: The disclosure illustrates a fish lure vocalization device which includes a main body defining an enclosed chamber inside. A vocalization module, a control module and a battery are disposed in the chamber. The vocalization module has a box in which an electromagnet and a metal diaphragm are disposed. The control module is used to control the electromagnet. A magnet is disposed on the metal diaphragm. The magnet is attracted by the electromagnet after the magnetic force is produced by electrifying the electromagnet, to deform the metal diaphragm to make sound. Thereby, the purpose of luring the fish to take the bait may be achieved.

Abstract: A fishing lure power charging device includes a body. A circuit board is assembled in the body. The circuit board has a power switching circuit and a charging circuit. A light emitter is assembled in the body and electrically connected to the power switching circuit, so that the light emitter emits light when the light emitter is electrically conducted. A battery is assembled in the body and electrically connected to the charging circuit, so that the battery is chargeable. Two conductive members are electrically connected to the circuit board, separately assembled to the body, and exposed from the body. A light sensing switch is assembled to the body and electrically connected to the circuit board, so that the light sensing switch switches the two conductive members to conduct with the power switching circuit or the charging circuit based on the light illuminating on the light sensing switch.

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: A fishing lure light emitting device includes a body, a light guiding bar, and a light emitting member. The body has a holder. The light guiding bar is embedded in the body. One end of the light guiding bar has a light receiving portion connected in the holder. The light emitting member includes a base and a light emitter. The base is detachably inserted into the holder. The light emitter is received in the holder and faces the light receiving portion of the light guiding bar. Since the base can be detached from the holder of the body, the light emitting member can be assembled to different bodies.

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Abstract: The disclosure illustrates a fish lure vocalization device which includes a main body defining an enclosed chamber inside. A vocalization module, a control module and a battery are disposed in the chamber. The vocalization module has a box in which an electromagnet and a metal diaphragm are disposed. The control module is used to control the electromagnet. A magnet is disposed on the metal diaphragm. The magnet is attracted by the electromagnet after the magnetic force is produced by electrifying the electromagnet, to deform the metal diaphragm to make sound. Thereby, the purpose of luring the fish to take the bait may be achieved.

Abstract: A fishing lure light emitting device includes a body, a light guiding bar, and a light emitting member. The body has a holder. The light guiding bar is embedded in the body. One end of the light guiding bar has a light receiving portion connected in the holder. The light emitting member includes a base and a light emitter. The base is detachably inserted into the holder. The light emitter is received in the holder and faces the light receiving portion of the light guiding bar. Since the base can be detached from the holder of the body, the light emitting member can be assembled to different bodies.

Abstract: A fishing lure power charging device includes a body. A circuit board is assembled in the body. The circuit board has a power switching circuit and a charging circuit. A light emitter is assembled in the body and electrically connected to the power switching circuit, so that the light emitter emits light when the light emitter is electrically conducted. A battery is assembled in the body and electrically connected to the charging circuit, so that the battery is chargeable. Two conductive members are electrically connected to the circuit board, separately assembled to the body, and exposed from the body. A light sensing switch is assembled to the body and electrically connected to the circuit board, so that the light sensing switch switches the two conductive members to conduct with the power switching circuit or the charging circuit based on the light illuminating on the light sensing switch.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

Abstract: An LED driving circuit and a light-emitting apparatus thereof are provided. The driving circuit includes a voltage providing unit, a voltage setting unit, a current feedback unit and a current dithering unit. The voltage providing unit receives a voltage setting signal and an input voltage to provide an emission driving voltage to a first terminal of an LED string. The voltage setting unit receives an emission feedback signal to provide a voltage setting signal. The current feedback unit provides the emission feedback signal and sequentially receives current setting voltages to sequentially set a driving current flowing through the LED string according to the current setting voltages. The current dithering unit receives the backlight control signal to sequentially provide the current setting voltages.

Abstract: A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: Methods of patterning a target material layer are provided herein. The method includes steps of positioning a semiconductor wafer having the target material layer thereon in an etch chamber and of providing a flow of etch gases into the etch chamber, the flow of etch gases etchant gas comprising a plurality of gases. The semiconductor wafer has a patterned hardmask feature formed from a compound on the target material layer. The method also includes steps of etching the target material layer using the patterned hardmask feature as a mask feature, wherein one of the gases chemically alters the patterned hardmask feature and at least one of the gases chemically repairs the patterned hardmask feature so that the patterned hardmask feature retains its dimensions during the etching. Associated semiconductor wafer are also provided herein.