Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.

Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.

Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.

Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.

Abstract: Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.

Abstract: A semiconductor structure comprising a substrate, a drift layer, at least a doping region, an epitaxial channel, a gate oxide layer, a gate metal and an isolation layer is provided. The drift layer is disposed on the substrate. The doping region comprises a p-well region, an n+ region and a p+ region, wherein the n+ region and a portion of p+ region are disposed in the p-well region which is adjacent to the n+ region. The epitaxial channel is disposed over the drift layer and covers at least a portion of the n+ region. The epitaxial channel is composed of at least two epitaxial layers whose conduction types or doping concentrations are not identical. The gate oxide layer is disposed on the epitaxial channel. The gate metal is disposed on the gate oxide layer. The isolation layer is disposed on the gate metal and the gate oxide layer.

Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.

Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.

Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.

Abstract: A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.

Abstract: A step trench metal-oxide-semiconductor field-effect transistor comprises a drift layer, a first semiconductor region, a stepped gate and a floating region. The drift layer is of a first conductivity type. The first semiconductor region is of a second conductivity type and located on the drift layer, wherein the drift layer and the first semiconductor region have a stepped gate trench therein. The stepped gate trench at least comprises a first recess located in the first semiconductor region and extending into the drift layer and a second recess located below a bottom of the first recess, wherein a width of the second recess is smaller than a width of the first recess. A floating region is of the second conductivity type and located in the drift layer below the second recess.

Abstract: A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 ?m.

Abstract: A SiC-based trench-type Schottky device is disclosed. The device includes: a SiC substrate having first and second surfaces; a first contact metal formed on the second surface and configured for forming an ohmic contact on the substrate; a drift layer formed on the first surface and including a cell region and a termination region enclosing the cell region; a plurality of first trenches with a first depth formed in the cell region; a plurality of second trenches with a second depth less than the first depth; a plurality of mesas formed in the substrate, each defined between neighboring ones of the trenches; an insulating layer formed on sidewalls and bottoms of the trenches; and a second contact metal formed on the mesas and the insulating layer, extending from the cell region to the termination region, and configured for forming a Schottky contact on the mesas of the substrate.

Abstract: A SiC-based trench-type Schottky device is disclosed. The device includes: a SiC substrate having first and second surfaces; a first contact metal formed on the second surface and configured for forming an ohmic contact on the substrate; a drift layer formed on the first surface and including a cell region and a termination region enclosing the cell region; a plurality of first trenches with a first depth formed in the cell region; a plurality of second trenches with a second depth less than the first depth; a plurality of mesas formed in the substrate, each defined between neighboring ones of the trenches; an insulating layer formed on sidewalls and bottoms of the trenches; and a second contact metal formed on the mesas and the insulating layer, extending from the cell region to the termination region, and configured for forming a Schottky contact on the mesas of the substrate.

Abstract: Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.

Abstract: A step trench metal-oxide-semiconductor field-effect transistor comprises a drift layer, a first semiconductor region, a stepped gate and a floating region. The drift layer is of a first conductivity type. The first semiconductor region is of a second conductivity type and located on the drift layer, wherein the drift layer and the first semiconductor region have a stepped gate trench therein. The stepped gate trench at least comprises a first recess located in the first semiconductor region and extending into the drift layer and a second recess located below a bottom of the first recess, wherein a width of the second recess is smaller than a width of the first recess. A floating region is of the second conductivity type and located in the drift layer below the second recess.

Abstract: A SiC trench gate transistor with segmented field shielding region is provided. A drain region of a first conductivity type is located in a substrate. A first drift layer of the first conductivity type is located on the substrate and a second drift layer of the first conductivity type is located on the first drift layer. A base region of a second conductivity type is located on the second drift layer. A gate trench is located between the adjacent base regions. A plurality of segmented field shielding regions of the second conductivity type is placed under a bottom of the gate trench and the space between segmented field shielding regions is the first drift region. A gate dielectric layer is located on a bottom and at a sidewall of the gate trench and a trench gate is formed in the gate trench.

Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.

Abstract: A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.

Abstract: A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 um.