Abstract: A 3-D multi-wafer stacked semiconductor structure and method for manufacturing the same. The method comprises steps of: providing a first wafer, a first circuit layer being formed on a surface thereof; bonding the first circuit layer with a carrier; performing a first thinning process on the first wafer; forming a first mask on the other surface of the thinned first wafer; providing a second wafer, a second circuit layer being formed on a surface thereof; bonding the second circuit layer with the first mask; and forming at least a through via filled with a conductor to electrically connect a first connecting pad on the first circuit layer and a second connecting pad on the second circuit layer.

Abstract: A method for fabricating a thin film bulk acoustic resonator (FBAR) is able to simplify the conventional fabricating step. Particularly, a chamber is defined between a substrate and of the resonator without need for a polishing processes and filling processes. Therefore, the present invention is able to have a high fabricating ability, a high production rate and a short fabricating time.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an adhesion layer 130 composed of poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: A method for fabricating bipolar transistor having insitu-formed epitaxial base is disclosed herein, the method including the following steps. The first step of the key feature according to one preferred embodiment of the present invention is to use a first epitaxial process to selectively grow an epitaxial collector layer in the etched first oxide layer. The first oxide layer is formed on a buried layer, which is formed on the silicon substrate. Then utilize a second epitaxial process to subsequently grow a first epitaxial-base layer and a second epitaxial-base layer. Particularly the second epitaxial process and the first epitaxial process are performed insitu. Then a patterned oxide layer and poly silicon layer are formed on the second epitaxial-base layer. Followed by etching the poly silicon layer and the patterned oxide layer, the second epitaxial-base layer is implanted, which together with the first epitaxial-base layer are etched.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line.

Abstract: A method for fabricating a thin film bulk acoustic resonator (FBAR) is able to simplify the conventional fabricating step. Particularly, a chamber is defined between a substrate and of the resonator without need for a polishing processes and filling processes. Therefore, the present invention is able to have a high fabricating ability, a high production rate and a short fabricating time.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using a rapid thermal anneal process, Ni 40 is transformed to NiSi at about 600° C. without any agglomeration. The method comprises forming a polysilicon layer 30 over a substrate 10. The surface 34 of the polysilicon layer is activated. Nickel 40 is selectively electroless deposited onto the surface of the polysilicon layer forming a Nickel layer over the polysilicon layer. The Ni layer 40 is rapidly thermally annealed forming a Nickel silicide layer 36 over the polysilicon layer 30. The rapid thermal anneal is performed at a temperature of about 600° C. for a time of about 40 sec. The Nickel silicide layer 36 preferably comprises NiSi 36B with a low resistivity.

Abstract: A method for fabricating bipolar transistor frequently used in high frequency circuit is disclosed herein. The foregoing method includes the following steps. First, a first oxide layer is formed on a p-type substrate, followed by developing a first photoresist pattern on the first oxide layer. A first, doped region is formed in the exposed substrate by a first implanting step. The first doped region comprises a n+ buried layer. Stripping of the first photoresist pattern, and annealing of the n+ buried layer follow. Removal of the first oxide layer to expose the n+ buried layer and a portion of the p-type substrate follows thereafter. These steps are followed by growing a first epitaxial layer on the n+ buried layer and a portion of the substrate, then a second epitaxial layer is formed on the first epitaxial layer. The first epitaxial layer is made of epitaxial n-type silicon, and the second epitaxial layer is made of in situ epitaxial p-type SiGe.

Abstract: Base layer formation without the use of selective epitaxial deposition is described. The process begins with the deposition of a seed layer of polysilicon over both the field oxide and the wafer surface that lies between them. An opening in said seed layer is then formed, between the areas of field oxide (and overlying an N+ buried layer). Non-selective epitaxial growth is then used to deposit the transistor's base layer. This automatically results in the formation of self aligned butted contacts of polysilicon on either side of the base. Manufacture of the transistor is completed in the usual way—emitter formation, emitter poly contact formation, ILD deposition, etc.

Abstract: A process for fabricating a bipolar junction transistor, (BJT), featuring reduced junction capacitance, resulting from the decreased dimensions of extrinsic, and intrinsic base, regions, has been developed. The BJT device, is comprised with only a single polysilicon level, used for the emitter structure, while an extrinsic base, and intrinsic base region, are accommodated in an epitaxial silicon layer, grown on an underlying silicon, active device region, and grown on a silicon seed layer, which in turn overlays insulator isolation regions. A boron doped, intrinsic base region can be formed in an undoped version of the epitaxial silicon layer, or the boron doped, intrinsic base region can be contained in the as deposited, epitaxial silicon layer, or contained in an as deposited, epitaxial, silicon-germanium layer.

Abstract: The invention provides three embodiments for forming Cu/Au contacts and interconnects using electroless deposition. The three embodiments have different adhesion and barrier layers for the electroless Cu or Au plugs. The invention discloses a technique of utilizing electroless deposition in USLI circuits. This metalization process is an additive and selective to provide conducting layers as well as an interconnection between layers of a multilevel conductive metal semiconductor device. The first embodiment uses adhesion layers formed of Ni, Al, polysilicon or PdSix; and a barrier layer composed of Ni—B, Ni, Pd, or Co and has first and second metal plugs formed by selective Cu or Au electroless processes. The second embodiment forms adhesion layers of PdSix. The third embodiment forms adhesion layers of activated Ti or Al. Cu or Au plugs are selectively electroless deposited to form interconnects.

Abstract: Method and baths for electroless depositing Cu on a semiconductor chip using four preferred Cu electroless baths. All four preferred electroless baths use hypophosphite as a reducing agent. The 4 baths use the following mediators (1) Nickel sulfate, (2) Pd Sulfate (3) Co Sulfate (4) Fe Sulfite, and complexing agents (Na Citrite, Boric Acid, Ammonium Sulfite). The baths can operate at a pH between 8 and 10. The invention forms high purity Cu interconnects having adequate step coverage to form in a hole having an aspect ratio greater than 2.7 to 1.

Abstract: The present invention provides a method of manufacturing an inductor element 46 using an electroless Au plating solution. The invention has three embodiments for forming the inductor. In the first embodiment, a first insulating layer 30 is formed over a semiconductor structure 10 20. An adhesion layer 34 composed of polysilicon is formed over the first insulating layer 30. A first barrier layer 36 comprised of Ni is selectively formed using an Ni electroless plating process over the adhesion layer 34. In an important step, a gold layer 40 is electroless plated over the first barrier layer 36 using an Au electroless plating process. A second barrier layer 44 is formed over the gold layer 40 using an electroless Ni deposition technique. A planarization layer is formed over the second barrier layer. A novel core metal layer composed of a Fe--Co alloy is electroless plated over the planarization layer.

Abstract: A method for fabricating a copper containing integrated circuit structure within an integrated circuit, and the copper containing integrated circuit structure formed through the method. There is first provided a substrate layer. There is then formed through a first electroless plating method a nickel containing conductor layer over the substrate layer. There is then activated the nickel containing conductor layer to form an activated nickel surface of the nickel containing conductor layer. Finally, there is then formed through a second electroless plating method a copper containing conductor layer upon the nickel containing conductor layer. Optionally, there may be formed a polysilicon layer over the substrate prior to forming the nickel containing conductor layer over the substrate, where the nickel containing conductor layer is formed upon the polysilicon layer. Optionally, there may also be formed a second nickel containing conductor layer upon the copper containing conductor layer.

Abstract: A method for fabricating a copper containing integrated circuit structure within an integrated circuit, and the copper containing integrated circuit structure formed through the method. There is first provided a substrate layer. There is then formed through a first electroless plating method a nickel containing conductor layer over the substrate layer. There is then activated the nickel containing conductor layer to form an activated nickel surface of the nickel containing conductor layer. Finally, there is then formed through a second electroless plating method a copper containing conductor layer upon the nickel containing conductor layer. Optionally, there may be formed a polysilicon layer over the substrate prior to forming the nickel containing conductor layer over the substrate, where the nickel containing conductor layer is formed upon the polysilicon layer. Optionally, there may also be formed a second nickel containing conductor layer upon the copper containing conductor layer.

Abstract: A process for preparing a solder bump can be prepared by the following procedure. The chip package was cleaned with an alkali or acid solution followed by Zn displacement (zincating)in a displacement solution which comprises NaOH, Z.sub.n o, potassium sodium tartrate and sodium nitrate. After zinc displacement the chip package was performed the electroless Ni--Cu--P deposit in the strong reducing solution which contains NaH.sub.2 PO.sub.2. The chip package deposited with Ni--Cu--P was then dipped into an organic solution as flux which is a mixture of the stearic acid and glutamic acid. Finally, dip soldering of the Ni--Cu--P deposited chip packages in a molten solder bath at a temperature 40.degree..about.80.degree. C. higher than the melting point of the corresponding Pb--Sn alloy.

Abstract: A process for manufacturing a vertical gate-enhanced bipolar transistor is described. The process does not require the presence of an insulating substrate to electrically isolate devices and is suitable for both NPN as well as PNP bipolar transistors. The process begins with the formation of a buried layer. This layer is accessed from the surface through a suitable well region. Then a trench, shaped as a hollow square is formed, lined with a layer of gate oxide and then filled with low resistivity polysilicon to form the gate. A polysilicon emitter layer is formed in the interior of the square, following implantation of arsenic ions with thermal drive-in to form an emitter junction just below the surface. After formation of the emitter junction, isolation layers, including self-aligned spacers, are constructed to cover the polysilicon emitter layer. Another layer of polysilicon is then laid down and then boron ions are implanted. This is followed by a thermal drive-in to form a base contact.