Abstract: Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.

Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Abstract: An exemplary semiconductor structure includes a semiconductor substrate; a plurality of metal lines on top of the semiconductor substrate, each line having a line width 5 nanometers or less: a plurality of dielectric features adjacent to the metal lines; and a plurality of metal vias on top of the metal lines. Out of a random sample of 1000 vias at least 950 vias are fully-aligned to corresponding metal lines.

Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Abstract: Embodiments of the invention include a method of forming portions of a multi-layer integrated circuit (IC) structure. The method includes forming a back-end-of-line (BEOL) layer having a BEOL layer topography. An etch-stop layer is formed over the BEOL layer topography. A metal is formed over the etch-stop layer. A first planarization operation is applied to remove a first portion of the metal. The etch-stop layer is used to stop the first planarization operation. A second planarization operation is applied to remove the etch-stop layer and a second portion of the metal.

Abstract: Self-aligned semiconductor device structures and techniques for fabrication thereof are provided. In one aspect, a self-aligned semiconductor device structure includes: at least one first conductive element embedded in a first dielectric; a second dielectric disposed selectively on the first dielectric relative to the at least one first conductive element; and at least one second conductive element present in the second dielectric that is fully aligned with the at least one first conductive element. A liner can be disposed on the second dielectric and which separates the second dielectric from the at least one second conductive element. A method of forming a self-aligned semiconductor device structure is also provided.

Abstract: Embodiments of the invention include a method of forming an integrated circuit having a single-damascene line-via interconnect. The method includes forming a via trench in a first dielectric layer. A first portion of a barrier layer is formed within the via trench, and a second portion of the barrier layer is formed over the first dielectric layer. A conductive region is formed and includes a conductive via element and a conductive via overburden. The conductive via element is within the via trench; a first portion of the conductive via overburden is over the second portion of the barrier layer; and a second portion of the conductive via overburden is over the conductive via. Planarization is applied to the conductive region and stopped at the second portion of the barrier layer. The conductive via element is coupled at a line-via interface to a conductive line of the single-damascene line-via interconnect.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect.

Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

Abstract: An apparatus that includes a solution bath of a seasoned solution, the seasoned solution containing a mixture of hydrofluoric acid, nitric acid, and acetic acid; and one or more silicon wafers being suspended in a position above the solution bath, wherein at least a portion of the mixture having been used in thinning the one or more silicon wafers.

Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

Abstract: Chamfer-less via interconnects and techniques for fabrication thereof with a protective dielectric arch are provided. In one aspect, a method of forming an interconnect includes: forming metal lines in a first dielectric; depositing an etch stop liner onto the first dielectric; depositing a second dielectric on the etch stop liner; patterning vias and a trench in the second dielectric, wherein the vias are present over at least one of the metal lines, and wherein the patterning forms patterned portions of the second dielectric/etch stop liner over at least another one of the metal lines; forming a protective dielectric arch over the at least another one of the metal lines; and filling the vias/trench with a metal(s) to form the interconnect which, due to the protective dielectric arch, is in a non-contact position with the at least another one of the metal lines. An interconnect structure is also provided.

Abstract: Various methods and structures for fabricating BEOL metallization layer including at least one bulk cobalt contact, the at least one bulk cobalt contact including a replacement non-cobalt metal cap integral to the at least one bulk cobalt contact. The method includes performing selective deposition, by a chemical exchange reaction of metal between a non-cobalt metal and Cobalt in the at least one bulk cobalt contact, of the replacement non-cobalt metal cap integrally formed in a top surface region of the bulk cobalt contact.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for forming interconnects using a conductive spacer configured to prevent a short between a via and an adjacent line. In a non-limiting embodiment of the invention, a first conductive line and a second conductive line are formed in a metallization layer. A conductive spacer is formed on the first conductive line and a conductive via is formed on a surface of the conductive spacer. The conductive via is positioned such that the conductive spacer is between the first conductive line and the conductive via. A height of the conductive spacer is selected to provide a predetermined distance from the conductive via to the second conductive line. The predetermined distance from the conductive via to the second conductive line is sufficient to prevent a short between the conductive via and the second conductive line.

Abstract: Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.

Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.

Abstract: A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.

Abstract: Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.