Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include one or more metal filled via structures within a dielectric layer of an interconnect level, wherein at least one of the metal filled via structures includes a bulk metal and a metal alloy overlaying the bulk metal, wherein the bulk metal and metal alloy filled via is coupled to an active circuit.

Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include one or more metal filled via structures within a dielectric layer of an interconnect level, wherein at least one of the metal filled via structures includes a bulk metal and a metal alloy overlaying the bulk metal, wherein the bulk metal and metal alloy filled via is coupled to an active circuit.

Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.

Abstract: Methods are provided for patterning an active region formed in a semiconductor wafer. In one aspect, the methods generally include providing active regions and kerf regions between active regions in the semiconductor wafer, wherein the active regions and the kerf regions include a patterned dielectric layer, a metal conductor, and a liner layer between the dielectric layer and the metal conductor. An upper surface of the active regions and the kerf regions is planarized to form a planar surface. The metal conductor from the kerf regions is selectively removed to form a trench. An optically opaque layer is conformally deposited onto the semiconductor wafer to form a recessed alignment mark in the kerf regions. The active regions are then patterned using the recessed alignment mark in the kerf region.

Abstract: A substantially flat bottom electrode embedded in a dielectric for magnetoresistive random access memory (MRAM) devices includes pre-filling the contact via prior to filling the trench with tantalum nitride in a via/trench structure. The top surface of the substantially flat bottom electrode is coplanar to the top surface of the dielectric.

Abstract: Methods are provided for patterning an active region formed in a semiconductor wafer. In one aspect, the methods generally include providing active regions and kerf regions between active regions in the semiconductor wafer, wherein the active regions and the kerf regions include a patterned dielectric layer, a metal conductor, and a liner layer between the dielectric layer and the metal conductor. An upper surface of the active regions and the kerf regions is planarized to form a planar surface. The metal conductor from the kerf regions is selectively removed to form a trench. An optically opaque layer is conformally deposited onto the semiconductor wafer to form a recessed alignment mark in the kerf regions. The active regions are then patterned using the recessed alignment mark in the kerf region.

Abstract: A method and structure of forming an interconnect structure with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.

Abstract: BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure.

Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.

Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.

Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

Abstract: BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

Abstract: Semiconductor devices and methods to fabricate the devices are provided. For example, a semiconductor device includes a back-end-of-line (BEOL) structure formed on a semiconductor substrate. The BEOL structure further includes at least one metallization layer comprising a pattern of elongated parallel metal lines. The pattern of elongated metal lines comprises a plurality of metal lines having a minimum width and at least one wider metal line having a width which is greater than the minimum width.

Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.

Abstract: Embodiments of the invention are directed to a method of forming a memory element pillar. The method includes forming memory element stack layers, forming a conductive cap layer over the memory element stack layers, forming a conductive seal layer over the cap layer, and forming a conductive etch stop layer over the conductive seal layer, wherein the conductive etch stop layer comprises a substantially planar surface. A hardmask is formed over the substantially planar surface of the conductive etch stop layer, wherein the hardmask defines dimensions of the memory element pillar.

Abstract: A substantially flat bottom electrode embedded in a dielectric for magnetoresistive random access memory (MRAM) devices includes pre-filling the contact via prior to filling the trench with tantalum nitride in a via/trench structure. The top surface of the substantially flat bottom electrode is coplanar to the top surface of the dielectric.

Abstract: Various methods and structures for fabricating BEOL metallization layer including at least one bulk cobalt contact, the at least one bulk cobalt contact including a replacement non-cobalt metal cap integral to the at least one bulk cobalt contact. The method includes performing selective deposition, by a chemical exchange reaction of metal between a non-cobalt metal and Cobalt in the at least one bulk cobalt contact, of the replacement non-cobalt metal cap integrally formed in a top surface region of the bulk cobalt contact.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.