Abstract: Disclosed herein are a switching mode converter and a method for controlling thereof. The switching mode converter includes a switching element, a bootstrap capacitor, and a control unit. The switching element is connected between one side of a first semiconductor device, another side of the first semiconductor device is connected to a ground, and an input power. The bootstrap capacitor is configured such that one side of the bootstrap capacitor is connected to the one side of the first semiconductor device. The control unit controls the output current or output voltage of a common charge pump provided to the switching element and the bootstrap capacitor in order to control the charging state of the bootstrap capacitor and the gate voltage of the switching element.

Abstract: A circuit for driving an organic light emitting diode display includes a display panel that displays an image by using organic light emitting diodes disposed at intersection areas of a plurality of gate lines and a plurality of data lines; a threshold voltage detection control unit that supplies a precharge voltage by sequentially turning on transistors for threshold voltage detection, which are connected among the data lines and the organic light emitting diodes on the display panel, in units of horizontal lines, and enables threshold voltages to be detected; and a source driver that detects threshold voltages of all organic light emitting diodes arranged on a corresponding horizontal line, and repeats an operation, as necessary, for sampling/holding the detected threshold voltages through M sample/hold circuits, converting the sampled/held threshold voltages into digital signals, and storing the digital signals in a memory.

Abstract: Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique.

Abstract: A method for routing gamma voltages in a flat panel display that includes a plurality of source driver integrated circuits (SDICs) each having a plurality of gamma buffers. The method includes forming routing lines to route a plurality of gamma voltages; connecting the routing lines to output terminals of the gamma buffers; applying the reset gamma voltage to the gamma buffer of selected SDIC after selecting the SDIC in which the gamma voltage is required to be reset in consideration of heating values of the SDICs, and changing connection between a routing line corresponding to the selected gamma buffer and a tap point of a resistor string of the SDIC such that the connection corresponds to the reset gamma voltage.

Abstract: A liquid crystal display driving circuit and method. A data register block of a controller applies in advance a polarity control signal to data before the data are stored in latches of a data driver, exchanges the data, and then stores the exchanged data in the latches. Thereby, it is possible to provide multiplexers, which are otherwise required for respective channels, to one controller and to decrease the size of a chip.

Abstract: A low dropout (LDO) circuit capable of controlled startup and a method of controlling the same are disclosed herein. The LDO circuit includes an amplifier, a pass element, and a startup control circuit. The amplifier receives a feedback voltage determined by an output voltage and a predetermined reference voltage, and provides a first voltage determined by the feedback voltage and the reference voltage. The pass element is connected to an input power and an output node for providing the output voltage. The startup control circuit includes a current source, and forward one of the first voltage, provided by the amplifier based on the level of the output voltage, and a second voltage, generated using the current source, to the gate of the pass element.

Abstract: An LCD driving circuit includes a first buffer configured to have a terminal for a first voltage, a terminal for a second voltage and a terminal for an intermediate voltage between the first voltage and the second voltage, and be driven in a range from the first voltage to the intermediate voltage; and a second buffer configured to have a terminal for the first voltage, a terminal for the second voltage and a terminal for the intermediate voltage, and be driven in a range from the intermediate voltage to the second voltage. The terminal for the intermediate voltage of the first buffer and the terminal for the intermediate voltage of the second buffer are connected with each other, and the first voltage is a highest voltage, the second voltage is a lowest voltage, and the intermediate voltage is in a range from the first voltage to the second voltage.

Abstract: Disclosed is a liquid crystal display panel driving circuit for driving a liquid crystal display panel with a resolution of N bits. N-bit digital data including upper X bits and lower Y bits is inputted. The liquid crystal display panel driving circuit includes a resistor string unit according to areas, a DAC converter switching unit according to areas, and an interpolation amplifier. The resistor string unit outputs analog reference voltages at different ratios according to three areas. The DAC converter switching unit receives the N-bit digital data, selects (Y+1) analog voltages from the analog reference voltages based on the upper X bits, outputs the (Y+1) analog voltages, and outputs the (Y+1) analog voltages of different combinations based on the lower Y bits. The interpolation amplifier receives the (Y+1) analog voltages and generates an interpolated output voltage by setting weights for the (Y+1) analog voltages by using multi-factors.

Abstract: Provided is a technology for preventing noisy data from being displayed before valid data is inputted when power is turned on in a liquid crystal display.

Abstract: A power supply circuit of a liquid crystal display device includes a first positive polarity charge charging unit including a first capacitor connected to positive and negative power terminals through switches to charge a charge, a second positive polarity charge charging unit including a second capacitor connected to the positive power terminal and a ground terminal through switches to charge a charge, a first positive polarity charge loading unit loading the charge supplied through the positive power terminal to a negative polarity terminal, a second positive polarity charge loading unit loading the charge charged in the first capacitor to a negative polarity terminal, a third positive polarity charge loading unit loading the charge charged in the second capacitor, and a positive polarity charge charging/loading control unit outputting charging control signals with a same phase to the switches, and periodically or irregularly changing durations of the charging and loading control signals.

Abstract: A display driving circuit includes a buffer section, an N-dot switch circuit, a charge sharing switch circuit, and a sharing voltage level control switch circuit. The buffer section buffers a plurality of pixel driving signals outputted from a plurality of DACs. The N-dot switch circuit selects paths of the plurality of pixel driving signals outputted from the buffer section in response to a first path selecting signal or a second path selecting signal that is determined depending upon a dot inversion method, and switches the paths to a plurality of output terminals. The charge sharing switch circuit shares charges among the plurality of output terminals in response to a charge sharing control signal. The sharing voltage level control switch circuit controls charge sharing between the plurality of output terminals and a voltage level upon charge sharing, in response to a sharing voltage level control signal.

Abstract: Disclosed herein are a switching mode converter and a method for controlling thereof. The switching mode converter includes a switching element, a bootstrap capacitor, and a control unit. The switching element is connected between one side of a first semiconductor device, another side of the first semiconductor device is connected to a ground, and an input power. The bootstrap capacitor is configured such that one side of the bootstrap capacitor is connected to the one side of the first semiconductor device. The control unit controls the output current or output voltage of a common charge pump provided to the switching element and the bootstrap capacitor in order to control the charging state of the bootstrap capacitor and the gate voltage of the switching element.

Abstract: An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other.

Abstract: Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique.

Abstract: A pad layout structure of a driver IC chip to be mounted to a liquid crystal display panel. The pad layout structure includes power pad sections placed at respective four corners of the driver IC chip and each having a first power pad for supplying first power to the driver IC chip, a second power pad for supplying second power to the driver IC chip, a third power pad for supplying third power to the driver IC chip and a fourth power pad for supplying fourth power to the driver IC chip.

Abstract: A method for routing gamma voltages in a flat panel display that includes a plurality of source driver integrated circuits (SDICs) each having a plurality of gamma buffers. The method includes forming routing lines to route a plurality of gamma voltages; connecting the routing lines to output terminals of the gamma buffers; applying the reset gamma voltage to the gamma buffer of selected SDIC after selecting the SDIC in which the gamma voltage is required to be reset in consideration of heating values of the SDICs, and changing connection between a routing line corresponding to the selected gamma buffer and a tap point of a resistor string of the SDIC such that the connection corresponds to the reset gamma voltage.

Abstract: Disclosed is a power supply line in which a voltage drop generated in a resistance component of a metal line which delivers a power voltage is minimized so that the level of the power supply voltage delivered to a semiconductor chip becomes constant in the entire area of the semiconductor chip. The semiconductor chip includes: at least two power supply pads to which a power voltage applied from an external unit of the semiconductor chip is supplied; power supply main metal lines connected to each of the power supply pads; power supply branch metal lines extended from each of the power supply main metal lines to deliver a power voltage to a circuit in the semiconductor chip; and at least an electrostatic discharge (ESD) improvement dummy pad, wherein the ESD improvement dummy pad is electrically connected to the corresponding power supply main metal line and the corresponding power supply branch metal line to minimize a voltage drop.

Abstract: A display driving circuit and method is capable of minimizing the residual image of a display panel as well as consumption electric current. The display driving circuit generates driving signals corresponding to valid data and black data and transmits the driving signals to a display panel, and includes N data selection switches (where N is the integer), N buffers, N buffer output selection switches, and multiple charge sharing switches. The N data selection switches select one of the valid data and the black data. The N buffers buffer the signal selected by the respective data selection switches. The N buffer output selection switches switch outputs of the buffers to output the respective driving signals. The multiple charge sharing switches connect the neighboring pairs of the driving signals.

Abstract: A method of removing offsets between channels of a liquid crystal panel is provided. The method includes: alternately arranging first type output buffers and second type output buffers for driving the pixels in units of at least two rows of the pixels; and arranging the first type output buffers and the second type output buffers in units of at least two columns of the pixels so that the output buffers with types opposite to those of previous two columns are arranged. The second type output buffers are embodied by switching connections among the differential transistors and connections among the load transistors in the first type output buffers.

Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.