Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.

Abstract: Provided are a method of arranging gamma buffers capable of decreasing a Kelvin of a source driver included in a flat panel display and minimizing a temperature deviation between source drivers, and the flat panel display applying the method. The method of arranging a plurality of gamma buffers which are arranged in one or more source drivers to output corresponding gamma voltages, includes a step of calculating power consumptions of the gamma buffers, wherein the method further comprises one or more steps of: changing tab points of the gamma buffers by using the calculated power consumptions of the gamma buffers; and changing positions of the gamma buffers by using the calculated power consumptions of the gamma buffers.

Abstract: A method of removing offsets between channels of a liquid crystal panel is provided. The method includes: alternately arranging first type output buffers and second type output buffers for driving the pixels in units of at least two rows of the pixels; and arranging the first type output buffers and the second type output buffers in units of at least two columns of the pixels so that the output buffers with types opposite to those of previous two columns are arranged. The second type output buffers are embodied by switching connections among the differential transistors and connections among the load transistors in the first type output buffers.

Abstract: Provided are a semiconductor integrated circuit having a heat release pattern in a chip so as to release heat generated inside the chip and a system board having a heat release unit used to release heat generated inside the semiconductor integrated circuit. The semiconductor integrated circuit includes: one or more output pads directly connected to an output terminal having a heat release pattern; a power supply pad supplying power; and one or more dummy pads connected to a metal line for supplying power or an internal output terminal of an internal function block, wherein the heat release pattern includes a plurality of unit contacts at the output terminal or a plurality of strip contacts having an area of about or larger than the sum of two or more of the unit contacts.

Abstract: Provided is a driving circuit for a liquid crystal display which is suitable for reducing a chip size and has improved noise immunity in a circuit which uses a level shifter and is constructed with a channel array. The driving circuit includes: the level shifter which is disposed in a previous stage of a channel region and shifts up a level of a data signal output from a buffer to output the data signal to the channel region; and the channel region which processes an output data of the level shifter in a format requested by a system and outputs a final data in a high or low format, and wherein the level shifter is disposed in a region excluding the channel region.

Abstract: An improved CPU for preventing a program malfunction which is capable of preventing a malfunction of a program by resetting the CPU when an abnormal data is fetched from a memory due to a noise, which includes a program counter for designating an address of an instruction to be executed, a first instruction register for storing an instruction outputted from a memory by the program counter, a second instruction register for fetching an instruction stored in the first instruction register in accordance with a first internal clock signal, a third instruction register for fetching an instruction stored in the first instruction register in accordance with a second internal clock signal, a comparator, which is operated in accordance with an enable signal, for comparing whether instructions stored in the second instruction register and the third instruction register are identical, a reset controller for outputting a reset signal in accordance with an output signal from the comparator, an instruction decoder for deco

Abstract: An improved arithmetic logic operation circuit capable of advantageously reducing propagation delay due to a logic gate for obtaining a high speed arithmetic logic unit by minimizing the number of logic gates, which includes an even bit arithmetic logic unit cell for logically operating upon even bits of a first and second data and for generating a carry out signal in accordance with an inverted carry in signal, an inverted carry enable signal and an operation control signal, and an odd bit arithmetic logic unit cell for logically operating upon the odd bits of the first and second data and for generating a carry out signal in accordance with the carry in signal, a carry enable signal and the operation control signal.