Patents by Inventor Dana Lee

Dana Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Partial Block Erase For Open Block Reading In Non-Volatile Memory
    Publication number: 20160172045
    Abstract: A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.
    Type: Application
    Filed: July 8, 2015
    Publication date: June 16, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Pitamber Shukla, Henry Chin, Dana Lee, Cynthia Hsu
  • STORAGE PARAMETERS FOR A DATA STORAGE DEVICE
    Publication number: 20160162353
    Abstract: A method of operating a data storage device having a memory includes reading error location data associated with a first region of the memory. The memory includes the first region and a second region. The method also includes generating one or more parameters based on the error location data. The method includes receiving data to be written to the memory and encoding the data to produce a codeword. The method also includes partitioning the codeword based on the one or more parameters to generate a first portion and a second portion. The method further includes performing a write operation to store the first portion at the first region and to store the second portion at the second region.
    Type: Application
    Filed: March 16, 2015
    Publication date: June 9, 2016
    Inventors: ABHIJEET MANOHAR, DANIEL EDWARD TUERS, DANA LEE
  • Temperature accelerated stress time
    Patent number: 9361030
    Abstract: A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 7, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Daniel E. Tuers, Dana Lee, Henry Chin, Abhijeet Manohar
  • Systems and methods for lower page writes
    Patent number: 9355713
    Abstract: In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 31, 2016
    Assignee: SanDISK Technologies Inc.
    Inventors: Jianmin Huang, Bo Lei, Jun Wan, Gerrit Jan Hemink, Steven T. Sprouse, Dana Lee
  • Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory
    Publication number: 20160141046
    Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 19, 2016
    Inventors: Anubhav Khandelwal, Dana Lee, Abhijeet Manohar, Henry Chin, Gautam Dusija, Daniel Tuers, Chris Avila, Cynthia Hsu
  • Compensating source side resistance versus word line
    Patent number: 9343164
    Abstract: A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: May 17, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Huai-Yuan Tseng, Dana Lee, Shih-Chung Lee, Deepanshu Dutta, Arash Hazeghi
  • Read Scrub with Adaptive Counter Management
    Publication number: 20160124679
    Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventors: Yichao Huang, Chris Avila, Dana Lee, Henry Chin, Deepanshu Dutta, Sarath Puthenthermadam, Deepak Raghu
  • Non-volatile memory and method with peak current control
    Patent number: 9293173
    Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 22, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Yi-Chieh Chen, Farookh Moogat
  • Storage Module and Method for Using Healing Effects of a Quarantine Process
    Publication number: 20160055910
    Abstract: A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge.
    Type: Application
    Filed: October 9, 2014
    Publication date: February 25, 2016
    Applicant: SanDisk Technologies Inc.
    Inventors: Daniel E. Tuers, Dana Lee, Henry Chin, Abhijeet Manohar
  • TEMPERATURE ACCELERATED STRESS TIME
    Publication number: 20160054937
    Abstract: A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions.
    Type: Application
    Filed: October 9, 2014
    Publication date: February 25, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Daniel E. Tuers, Dana Lee, Henry Chin, Abhijeet Manohar
  • Adaptive initial program voltage for non-volatile memory
    Patent number: 9269444
    Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 23, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Henry Chin, Dana Lee
  • Erase speed adjustment for endurance of non-volatile storage
    Patent number: 9224494
    Abstract: Techniques are disclosed herein for erasing non-volatile storage. The erase has two or more phases. The first phase includes erasing a group of non-volatile storage elements at a first speed until the group of non-volatile storage elements pass a first verify level. The second phase is performed after the group of non-volatile storage elements pass the first verify level. The second phase includes erasing the group of non-volatile storage elements at a second speed that is less than the first speed until the group of non-volatile storage elements pass a second verify level that is lower than the first verify level. Erasing at the first speed results in a fast erase without significant risk of over-erasing the storage elements. Erasing at the second speed during the second phase prevents or reduces over-erasure which could damage the storage elements.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 29, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Henry Chin, Dana Lee
  • Systems and Methods for Lower Page Writes
    Publication number: 20150332759
    Abstract: In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
    Type: Application
    Filed: October 30, 2014
    Publication date: November 19, 2015
    Inventors: Jianmin Huang, Bo Lei, Jun Wan, Gerrit Jan Hemink, Steven T. Sprouse, Dana Lee
  • Word line defect detection and handling for a data storage device
    Patent number: 9158613
    Abstract: A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 13, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Seungjune Jeon, Idan Alrod, Eran Sharon, Dana Lee
  • Data recovery from blocks with gate shorts
    Patent number: 9152497
    Abstract: A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: October 6, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Abhijeet Manohar
  • Storage Module and Method for Improving Boot Time During Block Binary Searches
    Publication number: 20150261613
    Abstract: A storage controller is configured to find a last-written page in a block in a memory by sending a command to the memory to read a page of data, receiving at least some of the data from that page, and analyzing the at least some of the data from that page to determine if that page is a written page. In one embodiment, the storage controller instructs the memory to read the page of data using a sense time that is shorter than a sense time used to read a page of data in response to a read request from a host controller. Additionally or alternatively, the amount of the data received by the storage controller can be less than the amount of data received when reading a page of data in response to a read request from a host controller.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 17, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Daniel E. Tuers, Dana Lee, Abhijeet Manohar, Yosief Ataklti
  • Compensating Source Side Resistance Versus Word Line
    Publication number: 20150255166
    Abstract: A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.
    Type: Application
    Filed: February 18, 2015
    Publication date: September 10, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Huai-Yuan Tseng, Dana Lee, Shih-Chung Lee, Deepanshu Dutta, Arash Hazeghi
  • ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE
    Publication number: 20150212883
    Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
    Type: Application
    Filed: April 8, 2015
    Publication date: July 30, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Wenzhou Chen, Zhenming Zhou, Jun Wan, Deepanshu Dutta, Yi-Chieh Chen, Dana Lee
  • PROGRAMMING AND VERIFYING FOR NON-VOLATILE STORAGE
    Publication number: 20150206593
    Abstract: Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when a present program-verify iteration is less than a threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the present program-verify iteration is greater than or equal to the threshold corresponding to the target data state that the storage element is being programmed to.
    Type: Application
    Filed: September 22, 2014
    Publication date: July 23, 2015
    Inventors: Anubhav Khandelwal, Dana Lee, Henry Chin, LanLan Gu
  • Reducing the impact of interference during programming
    Patent number: RE45813
    Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 24, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Dana Lee, Emilio Yero