Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

Abstract: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

Abstract: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

Abstract: In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract: The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program/verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.

Abstract: In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these.

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them.

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.