Abstract: A computer system implements hot mirroring for main system memory. That is, the computer system permits a user to hot plug a new memory board into the system and the system will respond by switching to a mirrored memory mode in which write cycles are performed to both memory boards (new and old). Once a new board is hot plugged into the system, the contents of the old board are copied over, in a background mode, to the new board so that both boards will have the same data. Because this background copying process may take a non-trivial amount of time and may detrimentally interfere with other system traffic, the system a user to exert control over the relative speed of the background copying so as to trade-off the time it takes to switch over to the mirroring mode versus the impact on on-going system behavior.

Abstract: A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Abstract: A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Abstract: The specification may disclose a computer system that may have two memory boards operated in a mirrored mode. The computer system may have the ability to operate in a mirrored mode with the memory boards having varying amounts of memory. This feature may allow for adding main memory to the computer system while the computer system is operational.

Abstract: A computer system implements hot mirroring for main system memory. That is, the computer system permits a user to hot plug a new memory board into the system and the system will respond by switching to a mirrored memory mode in which write cycles are performed to both memory boards (new and old). Once a new board is hot plugged into the system, the contents of the old board are copied over, in a background mode, to the new board so that both boards will have the same data. Because this background copying process may take a non-trivial amount of time and may detrimentally interfere with other system traffic, the system a user to exert control over the relative speed of the background copying so as to trade-off the time it takes to switch over to the mirroring mode versus the impact on on-going system behavior.

Abstract: The specification discloses a server system implementing hot pluggable memory boards in an architecture using X86 processors and off-the-shelf operating system, such as Windows® or Netware, which do not support hot plugging operations. Thus, the specification discloses systems and related methods for hot plugging main memory boards transparent to, and without the help of, the operating system. The operating system need only have the ability to recognize additional memory in order to use it. Moreover, the specification discloses a related set of memory error detection and correction techniques, again which are implementing transparent to, and without the help of, the operating system.

Abstract: A computer system, bus interface unit, and method are provided for securing certain Plug and Play peripheral devices connected to an ISA bus. Those devices include any device which contains sensitive information or passwords. The device may be encompassed by or interfaced through adapter cards which can be readily inserted into sockets and thereafter relocated to dissimilar sockets. A security device within the bus interface unit keeps track of identifying information of various Plug and Play ISA devices inserted and re-inserted into slots connected to the ISA bus. As a peripheral device or card is moved, an identifying number associated with that device is maintained in a device identification register within the bus interface unit. Moreover, the base address of that device address space is also maintained in I/O address registers contained within the bus interface unit. The device identification registers and I/O address registers are deemed shadowing registers to which future ISA cycles are compared.

Abstract: A computer system, bus interface unit, and method are provided for securing certain devices connected to an I2C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I2C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I2C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I2C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I2C bus or addressed device thereon.

Abstract: A computer system, bus interface unit, and method are provided for securing certain Plug and Play peripheral devices connected to an ISA bus. Those devices include any device which contains sensitive information or passwords. The device may be encompassed by or interfaced through adapter cards which can be readily inserted into sockets and thereafter relocated to dissimilar sockets. A security device within the bus interface unit keeps track of identifying information of various Plug and Play ISA devices inserted and re-inserted into slots connected to the ISA bus. As a peripheral device or card is moved, an identifying number associated with that device is maintained in a device identification register within the bus interface unit. Moreover, the base address of that device address space is also maintained in I/O address registers contained within the bus interface unit. The device identification registers and I/O address registers are deemed shadowing registers to which future ISA cycles are compared.

Abstract: A computer system, bus interface unit, and method is provided for programmably modifying securable resources of the computer. Those resources may be devices which can be coupled to peripheral buses of the computer, or which may contain or allow access to sensitive information that must be secured against improper access. The security system thereby functions to block accesses to certain devices based on the status of the user seeking access. Passwords stored in the security system are matched against locally and distally entered passwords from either the user of that particular computer system, an administrator of a subset of localized computer systems, or a system administrator in charge of all networked computer systems. The present security system is thereby hierarchical in nature and can be programmed by the system administrator such that the assignment of unlocked signals arising from password comparisons can be programmably mapped to various securable devices.

Abstract: A computer system according to the present invention implements a self-modifying “fail-safe” password system that allows a manufacturer or site administrator to securely supply a single-use password to users who lose a power-up password. The fail-safe password system utilizes at least one fail-safe counter, an encryption/decryption algorithm, a public key, and a secure non-volatile memory space. The fail-safe password is derived by generating a hash code using SHA, MD5,or a similar algorithm and encrypting the result. The fail-safe password is then communicated to the user. After the user enters the fail-safe password, the computer system generates an internal hash value and compares it with the hash code of the decrypted fail-safe password. When the decrypted fail-safe password matches the internal hash value, the user is allowed access to the computer system.

Abstract: An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.

Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

Abstract: A computer password security method employing a south bridge circuitry where the user password is compared to a secured password stored in secured memory which is directly accessible to the south bridge circuitry, removing any threat of data bus and/or unprotected memory snooping.

Abstract: In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic has been employed to work around the problems caused by the defective device. Higher device speeds and increasingly complex bus protocols have made the technique of singly using programmable logic, more difficult to implement. The addition of bidirectional switches integrated with and controlled by programmable logic in a monolithic integrated circuit allows the programmable logic device to respond more quickly while at the same time consuming less printed circuit board space. Additionally, the invention provides for termination of the isolated device and/or signal line stubs.

Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.