Abstract: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment.

Abstract: An illumination device and method for inspecting objects having microscopic features is provided. The device includes an illuminator which provides a solid angle of angularly specific illumination defining an illumination angle, selected by a user from among a continuous range of possible illumination angles. The device further includes an object inspector which inspects the object illuminated by the illuminator. The illuminator may include an illumination source, a light concentrator, an illumination angle selector, disposed along a light path between the illumination source and the object inspector. The illumination angle selector may have a first position in which directly-reflected light propagates toward the object plane and a second position in which no light both selected by the illumination angle selector and directly reflected from the object plane enters the collecting lens. Rather, in the second position, only scattered light from the object plane enters the collecting lens.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment.

Abstract: A new architecture for machine vision system that uses area sensor (or line sensor), with telecentric imaging optics compound with telecentric illumination module is described. The illumination module may include a bright field illumination source and/or a dark field illumination source. The telecentric imaging optics includes an upper imaging module having an aperture stop and a lower imaging module positioned between the upper imaging module and object, such that the light source and the aperture stop are located in the back focal plane of the lower imaging module. The lower imaging module images the illumination source into a plane of an aperture stop of the upper imaging module. The optical axis of the upper imaging module is offset with respect to the lower imaging module. The optical axis of the telecentric illumination module is offset with respect to the axis of the lower imaging module in the opposite direction.

Abstract: An illumination device and method for inspecting objects having microscopic features is provided. The device includes an illuminator which provides a solid angle of angularly specific illumination defining an illumination angle, selected by a user from among a continuous range of possible illumination angles. The device further includes an object inspector which inspects the object illuminated by the illuminator. The illuminator may include an illumination source, a light concentrator, an illumination angle selector, disposed along a light path between the illumination source and the object inspector. The illumination angle selector may have a first position in which directly -reflected light propagates toward the object plane and a second position in which no light both selected by the illumination angle selector and directly reflected from the object plane enters the collecting lens. Rather, in the second position, only scattered light from the object plane enters the collecting lens.

Abstract: Apparatus for high resolution processing of a generally planar workpiece having microscopic features to be imaged, comprising a video camera acquiring at least two candidate images of a microscopic portion on generally planar workpiece; a motion controller operative to effect motion, relative to the workpiece, of at least an optical element of the video camera along an optical axis extending generally normally to a location on a surface of the workpiece, the video camera acquiring the at least two candidate images at selected time intervals, each of the at least two candidate images differing by at least one image parameter; an image selector operative to select an individual image from among the at least two candidate images according to predefined criteria of image quality; and a selected image analyzer operative to analyze at least a portion of the individual image selected by the image selector.

Abstract: Devices allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. The device includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. One or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled to an associated bit line. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, responsively connect the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.

Abstract: A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry.

Abstract: The embodiments described herein allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. One embodiment includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. In various embodiments, one or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled to an associated bit line. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, responsively connect the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.

Abstract: Apparatus for high resolution processing of a generally planar workpiece having microscopic features to be imaged, comprising a video camera acquiring at least two candidate images of a microscopic portion on generally planar workpiece; a motion controller operative to effect motion, relative to the workpiece, of at least an optical element of the video camera along an optical axis extending generally normally to a location on a surface of the workpiece, the video camera acquiring the at least two candidate images at selected time intervals, each of the at least two candidate images differing by at least one image parameter; an image selector operative to select an individual image from among the at least two candidate images according to predefined criteria of image quality; and a selected image analyzer operative to analyze at least a portion of the individual image selected by the image selector.

Abstract: Method and apparatus for manufacture and inspection of flat articles, such as flat planel display substrates, that are manufactured in a contamination-sensitive environment. In particular, a manufacturing step such as applying coatings to the article is performed in a self-contained micro-environment, typically characterized by an airborn particulate concentration which is substantially lower than its surroundings. Automated inspection apparatus is provided inside the self-contained micro-environment of the fabrication equipment to inspect the article after completion of the fabrication step and before transfer of the article to other fabrication equipment. The inspection apparatus includes an illumination subsystem illuminating the article with various configurations of dark field and bright field illumination, a staring array sensor capturing images of the article under various illumination configurations and a computer that analyzes the images to automatically detect defects.

Abstract: An inspection illuminates a generally specular surface of an electrical circuit with flashes of light. The flashed light comes form at least two spectrally different sources, and is temporally spaced. A camera forms an optical image of the circuit for each flash of light. Optical images are combined to provide a combined image. An analysis of the combined image can detect defects, and production related decisions may be based on this analysis.

Abstract: An inspection illuminates a generally specular surface of an electrical circuit with flashes of light. The flashed light comes form at least two spectrally different sources, and is temporally spaced. A camera forms an optical image of the circuit for each flash of light. Optical images are combined to provide a combined image. An analysis of the combined image can detect defects, and production related decisions may be based on this analysis.

Abstract: A capacitance sensing technique for ferroelectric random access, memory devices and arrays which enables fast sensing operations to be performed allowing for low latency “read” operations and thereby providing overall system performance advantages. Through the use of the technique of the disclosed, concurrent polling and reading of data may be achieved prior to pulsing (or driving) the plate line. This then allows the memory “restore” function to be hidden behind the “read” data stream at the memory device output pins. In accordance with the technique of the present invention, the sensing may begin prior to pulsing the plate line and it is the sensing process itself which interrogates the memory and concurrently prepares the data for the outputs. In this manner, it is the pulsing of the plate line after the data is sensed that performs the “restore” and this operation is not a portion of the “read” access time critical path.

Abstract: A capacitance sensing technique for ferroelectric random access memory devices and arrays which enables fast sensing operations to be performed allowing for low latency “read” operations and thereby providing overall system performance advantages. Through the use of the technique of the disclosed, concurrent polling and reading of data may be achieved prior to pulsing (or driving) the plate line. This then allows the memory “restore” function to be hidden behind the “read” data stream at the memory device output pins. In accordance with the technique of the present invention, the sensing may begin prior to pulsing the plate line and it is the sensing process itself which interrogates the memory and concurrently prepares the data for the outputs. In this manner, it is the pulsing of the plate line after the data is sensed that performs the “restore” and this operation is not a portion of the “read” access time critical path.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.