Patents by Inventor David J. Clarke
David J. Clarke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942516Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.Type: GrantFiled: March 25, 2022Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Kanwaljit Singh, Hubert C. George, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts, James S. Clarke
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Publication number: 20230375600Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.Type: ApplicationFiled: May 15, 2023Publication date: November 23, 2023Inventors: David J. Clarke, Stephen Denis Heffernan, Nijun Wei, Alan J. O'Donnell, Patrick Martin McGuinness, Shaun Bradley, Edward John Coyne, David Aherne, David M. Boland
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Publication number: 20230366924Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.Type: ApplicationFiled: May 16, 2023Publication date: November 16, 2023Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
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Publication number: 20230221360Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: March 22, 2023Publication date: July 13, 2023Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11686763Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.Type: GrantFiled: February 28, 2022Date of Patent: June 27, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
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Patent number: 11668734Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.Type: GrantFiled: September 3, 2021Date of Patent: June 6, 2023Assignee: Analog Devices International Unlimited CompanyInventors: David J. Clarke, Stephen Denis Heffernan, Nijun Wei, Alan J. O'Donnell, Patrick Martin McGuinness, Shaun Bradley, Edward John Coyne, David Aherne, David M. Boland
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Patent number: 11644497Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: November 23, 2021Date of Patent: May 9, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20220252664Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.Type: ApplicationFiled: February 28, 2022Publication date: August 11, 2022Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
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Patent number: 11372030Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.Type: GrantFiled: June 5, 2020Date of Patent: June 28, 2022Assignee: Analog Devices International Unlimited CompanyInventors: David J. Clarke, Stephen Denis Heffernan, Alan J. O'Donnell, Patrick M. McGuinness
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Publication number: 20220082605Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11269006Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.Type: GrantFiled: October 2, 2020Date of Patent: March 8, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
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Publication number: 20210396788Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Inventors: David J. Clarke, Stephen Denis Heffernan, Nijun Wei, Alan J. O'Donnell, Patrick Martin McGuinness, Shaun Bradley, Edward John Coyne, David Aherne, David M. Boland
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Patent number: 11193967Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: January 15, 2020Date of Patent: December 7, 2021Assignee: Analog Devices GlobalInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11112436Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.Type: GrantFiled: March 21, 2019Date of Patent: September 7, 2021Assignee: Analog Devices International Unlimited CompanyInventors: David J. Clarke, Stephen Denis Heffernan, Nijun Wei, Alan J. O'Donnell, Patrick Martin McGuinness, Shaun Bradley, Edward John Coyne, David Aherne, David M. Boland
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Publication number: 20210088580Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.Type: ApplicationFiled: October 2, 2020Publication date: March 25, 2021Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
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Publication number: 20200400725Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.Type: ApplicationFiled: June 5, 2020Publication date: December 24, 2020Inventors: David J. Clarke, Stephen Denis Heffernan, Alan J. O'Donnell, Patrick M. McGuinness
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Patent number: 10794950Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.Type: GrantFiled: July 16, 2019Date of Patent: October 6, 2020Assignee: Analog Devices GlobalInventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
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Patent number: 10677822Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.Type: GrantFiled: September 19, 2017Date of Patent: June 9, 2020Assignee: Analog Devices Global Unlimited CompanyInventors: David J. Clarke, Stephen Denis Heffernan, Alan J. O'Donnell, Patrick M. McGuinness
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Publication number: 20200158771Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: January 15, 2020Publication date: May 21, 2020Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: D1021892Type: GrantFiled: November 25, 2020Date of Patent: April 9, 2024Assignee: Apple Inc.Inventors: Jody Akana, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Jeremy Bataillou, Daniel J. Coster, Daniele De Iuliis, M. Evans Hankey, Julian Hoenig, Richard P. Howarth, Jonathan P. Ive, Duncan Robert Kerr, Scott A. Myers, David A. Pakula, Rasamy Phouthavong, Matthew Dean Rohrbach, Peter Russell-Clarke, Benjamin Andrew Shaffer, Ashutosh Y. Shukla, Mikael Silvanto, Christopher J. Stringer, Eugene Antony Whang, Rico Zörkendörfer