Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.

Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Abstract: An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.

Abstract: Harsh electrical environments integrated circuit protection for system-level robustness and methods of forming the same are provided. In one embodiment, a protection system includes dual-polarity high blocking voltage primary and secondary protection devices each electrically connected to a pad. The primary protection device has a current handling capability greater than a current handling capability of the secondary protection devices, and the secondary protection device has a turn-on speed that is faster than a turn-on speed of the primary protection device so as to decrease pad voltage overshoot when a fast transient electrical event occurs on the pad. Additionally, the holding voltage of the primary protection device is less than a holding voltage of the secondary protection device such that once the primary protection device has been activated the primary protection device clamps the pad voltage so as to minimize a flow of high current through the secondary protection device.

Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract: An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.

Abstract: Harsh electrical environments integrated circuit protection for system-level robustness and methods of forming the same are provided. In one embodiment, a protection system includes dual-polarity high blocking voltage primary and secondary protection devices each electrically connected to a pad. The primary protection device has a current handling capability greater than a current handling capability of the secondary protection devices, and the secondary protection device has a turn-on speed that is faster than a turn-on speed of the primary protection device so as to decrease pad voltage overshoot when a fast transient electrical event occurs on the pad. Additionally, the holding voltage of the primary protection device is less than a holding voltage of the secondary protection device such that once the primary protection device has been activated the primary protection device clamps the pad voltage so as to minimize a flow of high current through the secondary protection device.

Abstract: A system of provisioning a mobile wireless communications device to display account or device specific characteristics includes a database for storing a plurality of display characteristics for different wireless carriers, electronic mail (email) service providers, and device types. A configuration module accesses the database and uploads the display characteristics of at least one of the wireless carrier, email service provider or device type to the mobile wireless communications device upon provisioning of the mobile wireless communications device to access email from a remote location.

Abstract: A system of provisioning a mobile wireless communications device to display account or device specific characteristics includes a database for storing a plurality of display characteristics for different wireless carriers, electronic mail (email) service providers, device types, and source mailbox mail domains. A configuration module accesses the database and uploads the display characteristics of at least one of the wireless carrier, email service provider, device type, or source mailbox mail domain to the mobile wireless communications device upon provisioning of the mobile wireless communications device to access email from a remote location.

Abstract: An electronic mail (email) server has a database that stores unique identifiers (UID's) of electronic messages. A proxy obtains mappings from the database for previously existing UID's of electronic messages that have been determined from a polling operation. A cache caches the mappings of UID's and the proxy is operative for purging the cache of the previously existing UID's after polling.

Abstract: An electronic mail (email) server includes a proxy that obtains mappings for unique identifiers (UID's) corresponding to new electronic messages that have been determined from a polling operation. A Least Recently Used (LRU) cache caches each new message and releases from cache least recently used messages. A memory in which all messages within the LRU cache are spooled.

Abstract: An electronic mail (email) server has a database that stores unique identifiers (UID's) of electronic messages. A proxy obtains mappings from the database for previously existing UID's of electronic messages that have been determined from a polling operation. A cache caches the mappings of UID's and the proxy is operative for purging the cache of the previously existing UID's after polling.

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

Abstract: Lipid vesicle particles capable of being targeted to a cell type of interest, said particle incorporating a peptide which is responsive to a predetermined metabolic signal from the targeted cell so as to modulate the permeability of the particle, said particle further incorporating a species to be targeted to the cell which is activated on said modulation of permeability. The particles may be used in methods for detecting cells, methods of treating cells and also therapeutically.

Abstract: An analysis for determining a characteristic cycle time of a sample. Active elements in the sample are excited with sufficient intensity and duration larger than the characteristic cycle time that at least some of the active elements are re-excited to an excited state substantially immediately following relaxation to a ground state, detecting quanta emitted by the active elements in the sample to obtain a detected signal, and analyzing the detected signal to derive the characteristic cycle time. The number of active elements in the sample and the intensity of the excitation are such that quanta are detected in a stream in which individual quanta are distinguishable from each other.

Abstract: A method of detecting an object located within a dynamic scattering media, includes i) directing a continuous coherent light wave of predetermined wavelength into the media; ii) detecting dynamically scattered light emerging from the media; iii) correlating the detected light photons in the time or frequency domain; iv) determining the presence of an object from analysis of differences between the correlation and a correlation which would arise from photons scattered by the media only; and v) determining the approximate position of the object within the media from the analysis of the correlation and knowledge of the mean transport path of the light wave of predetermined wavelength within the media.

Abstract: A process for detecting an analyte which process comprises (a) contacting a sample suspected of containing said analyte with a containment means comprising a barrier which separates signal generating reagents from said sample, in the presence of an element which interacts specifically with said analyte, under conditions whereby interaction between the analyte and the said element results in activation of the signal generating reagents within the containment means on the side of the barrier opposite to the sample, and (b) detecting any signal generated and retained within the containment means from the sample side of the barrier. The process of the invention provides for sensitive detection of very small numbers of analyte materials using measurement techniques which include counting methods such as flow cytometry.