Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR.

Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.