Abstract: A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.

Abstract: A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

Abstract: A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.

Abstract: An anti-reflective film for deep ultraviolet (DUV) photolithograghy includes silicon oxime having the formula Si(1−x+y+z)NxOy:H2, wherein x, y, and z represent the atomic percentage of nitrogen, oxygen, and hydrogen, respectively. The film is characterized by a substantial lack of bonding between silicon atoms and oxygen atoms, and has a thickness of less than approximately 600 Å which is selected to produce destructive interference between incident and reflected light at a selected DUV wavelength.

Abstract: A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

Abstract: A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.

Abstract: A mold (10) for molding thin resin sheets includes a center mold plate (12) and two side mold plates (14, 16) disposed on opposite sides of the center mold plate. The mold plates are oriented generally vertically and parallel to each other, and the side mold plates are narrowly spaced from the center mold plate to define a pair of generally vertical mold cavities (18, 20) on either side of the center mold plate. The side mold plates may optionally include recesses (51) in their generally planar mold surfaces (38, 40) adjacent at least one longitudinal edge of the plate, for molding thin resin sheets with integral edge flanges. The mold includes spacer strips (46, 47) for spacing the side mold plates a precise distance from the center mold plate and parallel thereto. The mold thus permits molding of thin resin sheets having precisely controlled uniform thickness.

Abstract: A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.

Abstract: A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure to overlie the semiconductor substrate. Thereafter, a thin mask layer is formed to overlie the ONO structure to protect the ONO structure during a selective etch of a thick mask layer. The thick mask layer is formed to overlie the thin mask layer to protect the ONO structure during boron and arsenic implants. Thereafter, an etch process is performed in the ONO structure and a silicon oxide layer is formed to fill the etched area. A chemical-mechanical-polishing process is performed to planarize the silicon oxide layer and to form a planar surface continuous with an upper surface of the thick mask layer. The planarized silicon oxide layer functions as a bit-line oxide layer.

Abstract: A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure overlying the semiconductor substrate. Thereafter, a hard mask layer is formed to overlie ONO structure, the hard mask layer having an upper surface. To form a trench for the buried bit-line, an etch process is performed on the ONO structure. Thereafter, silicon dioxide is deposited to fill the trench. To control a thickness of the deposited silicon dioxide, a chemical-mechanical-polishing process is performed to planarize the silicon dioxide and form a planar surface continuous with the upper surface of the hard mask layer. Finally, the hard mask layer is removed and the remaining silicon dioxide forms a uniform bit-line oxide layer.

Abstract: Photolithographic processing is enhanced by employing a composite comprising two bottom anti-reflective coatings, wherein the extinction coefficient (k) of the upper anti-reflective coating is less than that of the underlying anti-reflective coating. The use of a composite bottom anti-reflective coating comprising partially transparent upper anti-reflective coating substantially reduces reflective notching in the photoresist layer, particularly when employing i-line or deep UV irradiation to obtain sub 0.35 &mgr;m features.

Abstract: A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.

Abstract: A process for fabricating a semiconductor device includes the step of processing a patterned resist layer to vary the lateral dimensions of the patterned resist layer while forming doped regions in a semiconductor substrate. A graded junction profile is formed by creating a patterned resist layer having a first substantially vertical edge surface. A doping process is carried out to form a first doped region in the semiconductor substrate having a junction profile substantially continuous with the first substantially vertical edge surface. The patterned resist layer is processed to form a second substantially vertical edge surface, which is laterally displaced from the first substantially vertical edge surface. A doping process is carried out to form a second doped region having a junction profile that is substantially continuous with the second substantially vertical edge surface. The junction profiles of the first and second doped regions form a graded junction within the semiconductor substrate.

Abstract: At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

Abstract: A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.

Abstract: The laboratory countertop of the present invention utilizes a thin chemical and heat resistant surfacing panel in the form of a thin planar sheet made of a cured thermoset resin composition. In accordance with one broad aspect of the present invention, the thin chemical and heat resistant surfacing panel is mounted overlying a backing panel of a less expensive and lighter material such as particle board or plywood. The surfacing panel is of a cast, monolithic construction and has a width at least 50 times its thickness and a length at least 100 times its thickness. The surfacing panel can additionally include an edge flange integrally formed with the thin planar sheet. The edge flange hides the underlying backing panel from view and gives the countertop the appearance of a unitary thick slab.

Abstract: Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

Abstract: A system and method for providing a small device formed on a semiconductor is disclosed. The method and system include controlling the surface by providing a very thin oxide layer and providing a shallow implant through the very thin oxide layer.

Abstract: A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

Abstract: A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.