Abstract: A volatile memory device, in accordance with the present invention, includes an array of memory cells with at least two dummy cells disposed within the memory array. A driver is included for writing a first state to one of the at least two dummy cells and for writing a second state to another one of the at least two dummy cells. A comparison circuit compares the first state and the second state to a threshold to determine if a refresh of the array of memory cells is needed.

Abstract: A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.

Abstract: This invention concerns a system and method for securely distributing subsetted fonts from a distributor to a client. The system includes a signing module to construct an authentication tree having leaves formed of glyphs, one or more intermediate levels of nodes computed as one-way functions of the glyphs, and a root computed as a one-way function of the nodes. The signing module digitally signs the root of the authentication tree using a private signing key unique to the font creator or distributor. The system has a subsetting module to construct a font subset file that contains selected glyphs and other data to be included in a font subset. The font subset file also holds the digitally signed root of the font authentication tree and one or more authentication values of the authentication tree that represents non-selected glyphs and data of the font that are not contained in the font subset. The font subset file is distributed to requesting clients.

Abstract: A method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue are disclosed. The processor capable of out-of-order instruction issue includes an instruction cache having multiple cache lines. The instruction cache is coupled to an instruction buffer via a multiplexor. The instruction buffer includes several slots, and these slots are sequentially filled by instructions from the instruction cache under the supervision of the multiplexor. The slot in which the first instruction resides is dictated by a fetch address. Any empty slot in the instruction buffer will be filled with instructions from a subsequent cache line of the instruction cache if the first instruction does not reside in the first slot of the instruction buffer.

Abstract: A circuit for generating control signals used in a microprocessor has a storage array, such as a read-only memory (ROM) array, which contains a plurality of predefined logic patterns. An entry of the ROM array is selected, such as by the use of an address decoder, to choose a specific pattern, and the specific pattern is then modified based on a dynamic signal to generate an output control signal. The microprocessor may further predecode a base instruction using operation and operand source bits to yield a predecoded instruction having an address field whose value corresponds to the specific pattern. The dynamic signal can be based on whether an operand should be forwarded from a microprocessor component, and the specific pattern is then equivalent to a value for control signals required to execute an instruction when assuming that the operand should not be forwarded. Special control states can also be implemented, such as stall, halt, or scan data, through the use of particular code points in the ROM.

Abstract: The present invention relates to multiprocessors which has several microprocessors on a single chip. Efficiency is improved by stripping certain functions that are used less freely from the microprocessor and sharing these functions between several symmetric microprocessors. This method allows each CPU to occupy a smaller area while preserving complete symmetry of capability for software simplification. For example, the shared execution units can include the floating point unit and multimedia execution units.

Abstract: An improved multi-port SRAM that requires fewer access means, bit lines and sense amplifiers for multiport access. The number of access means can be reduced to ceiling (log.sub.2 B), where B is the number of access ports. The number of bit line sense amplifiers needed to achieve multiport access can also be reduced by the same factor as the number of access devices per cell. An efficient means is provided to select a correct access device among the plurality of access devices within the array and to condition a correct multiplexer select signal to couple a correct bit as specified by the port read address to the port read output. The access device selection can be implemented by a tree representation of all possible bit line and multiplexer select combinations. The tree representation can be implemented in hardware or software. Examples are provided of both a circuit and a tree walking algorithm that gives priority by port order.

Abstract: Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system.

Abstract: Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; sorting this list in the order of number of outputs controlled, i.e., touched in the forward trace; listing each unique combinational circuit output; sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs; when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.

Abstract: Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; soding this list in the order of number of outputs controlled, i.e. touched in the forward trace: listing each unique combinational circuit output: sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of tile same circuit outputs: when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.

Abstract: A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground).

Abstract: An error detection circuit having a plurality of interconnected modules such as field replaceable units, each of the modules being driven by a system clock such that a failed module propagates errors to other modules before the system clock can be stopped. Each of the modules has at least one error checker circuit for generating an error checker signal when an error occurs. Each module includes an error trigger which is set responsive to the detection of an error checker signal, with each error trigger forming the stage of a counter whose count identifies the error trigger which was first set. The counter formed by the error triggers is preferably a Galois field counter which starts to count only upon the receipt of a non-zero impulse to any of its stages, and whose final count contains a unique value which identifies the source of the first non-zero impulse.

Abstract: A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.

Abstract: Special control within a data processing system is signalled by a predetermined unique combination of data and error correcting code (ECC) bits. The predetermined combination, received from a source 1, is one which normally is decoded to indicate the presence of an uncorrectable error. A comparator 3 compares data bits held in a register 5 with a reference pattern of data bits held in a storage medium 7. At the same time, a syndrome generator 9 generates a syndrome from the received word, which syndrome is decoded by a syndrome decoder 11. If a particular flag syndrome sf (which is selected from the syndromes normally indicating the existence of an uncorrectable error) is detected, and comparator 3 indicates an equal comparison, AND 13 will provide a signal indicating that the unique combination has been received. It will also, through inverter 15 and AND 17 block transmission of an error indication to the system.

Abstract: Operations to prepare a secondary paging store for a data transfer relative to a central processor main store are overlapped in time with chaining operations of an input-output channel relative to the main store for preparing a command defining the transfer operation. In a preferred embodiment the paging store is organized for sequential access to page records and the operations to prepare the paging store include a calculation of a "roll mode" displacement factor which defines a randomly chosen displacement position in a designated page area for beginning the transfer with minimized latency. This factor is calculated as a function of channel operational characteristics as well as the bit timing rate of the paging store. The displacement calculation is also adapted for a paging store having different timing rates for transferring data and regenerating stored data.

Abstract: Latency of a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities is reduced without modification of the channel and CPU hardwares. The storage device is divided into a plurality of randomly accessible pages each having parallel cyclic tracks. Each page is subdivided into two sequentially and cyclically accessible Sectors 0 and Sector 1. Parallel bits on different tracks form bytes. Data are transferred byte by byte between a selected page of the device and a specified one-page data area in the main storage. A channel program is constructed using three commands (CCWs); a Seek Page command followed by two different Read or Write commands. At the end of the Seek Page operation, a control unit determines which of Sector 0 or 1 is more immediately accessible.