Patents by Inventor Debapriya Sahu
Debapriya Sahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113724Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.Type: ApplicationFiled: December 11, 2023Publication date: April 4, 2024Inventors: Debapriya SAHU, Pranav SINHA, Meghna AGRAWAL
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Patent number: 11936340Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.Type: GrantFiled: May 30, 2023Date of Patent: March 19, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rohit Chatterjee
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Patent number: 11888497Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.Type: GrantFiled: August 22, 2022Date of Patent: January 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Pranav Sinha, Meghna Agrawal
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Publication number: 20230396259Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Inventors: Debapriya SAHU, Rittu SACHDEV
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Patent number: 11777507Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: GrantFiled: July 15, 2022Date of Patent: October 3, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rittu Sachdev
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Publication number: 20230308053Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.Type: ApplicationFiled: May 30, 2023Publication date: September 28, 2023Inventors: Debapriya Sahu, Rohit Chatterjee
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Publication number: 20230275614Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Inventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
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Patent number: 11705867Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.Type: GrantFiled: March 9, 2022Date of Patent: July 18, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rohit Chatterjee
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Patent number: 11683066Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.Type: GrantFiled: June 16, 2021Date of Patent: June 20, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
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Publication number: 20230094295Abstract: A transmitter comprises an antenna array demultiplexor having a first input for an output signal, a second input for a control signal, a first output coupled to a first output pin, and a second output coupled to a second output pin. The antenna array demultiplexor provides the output signal to the first or second output based on the control signal. The first and second output pins are coupled to first and second antennae, respectively. In some implementations, the transmitter includes a transformer and a capacitor coupled in parallel between the first and second output pins, and the antenna array demultiplexor comprises a first switch coupled between the first output pin and a first ground pin, and a second switch coupled between the second output pin and a second ground pin. The first switch receives a second control signal, and the second switch receives an inverse of the second control signal.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Rohit CHATTERJEE, Debapriya SAHU
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Publication number: 20230047618Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.Type: ApplicationFiled: October 17, 2022Publication date: February 16, 2023Inventors: Meghna AGRAWAL, Debapriya SAHU
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Publication number: 20220407537Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.Type: ApplicationFiled: August 22, 2022Publication date: December 22, 2022Inventors: Debapriya SAHU, Pranav SINHA, Meghna AGRAWAL
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Publication number: 20220360269Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: ApplicationFiled: July 15, 2022Publication date: November 10, 2022Inventors: Debapriya SAHU, Rittu SACHDEV
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Publication number: 20220345138Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.Type: ApplicationFiled: June 1, 2021Publication date: October 27, 2022Inventors: Meghna AGRAWAL, Debapriya SAHU
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Patent number: 11476859Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.Type: GrantFiled: June 1, 2021Date of Patent: October 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Meghna Agrawal, Debapriya Sahu
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Patent number: 11424756Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.Type: GrantFiled: August 31, 2020Date of Patent: August 23, 2022Assignee: Texas Instruments IncorporatedInventors: Debapriya Sahu, Pranav Sinha, Meghna Agrawal
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Patent number: 11418201Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: GrantFiled: January 12, 2021Date of Patent: August 16, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rittu Sachdev
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Publication number: 20220200534Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Inventors: Debapriya Sahu, Rohit Chatterjee
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Patent number: 11303248Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.Type: GrantFiled: November 5, 2018Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rohit Chatterjee
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Patent number: 11303284Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.Type: GrantFiled: July 14, 2021Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rittu Sachdev