Abstract: In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.

Abstract: EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal amount of current, but in opposite direction, is caused to be flown in another pin (“third pin”) located close to the load pin. As a result, the EMI caused by the third pin cancels the EMI generated by the load pin. During a discharge phase, a fourth pin carries and equal amount of current, but in opposite direction, to that in the load pin. The third and fourth pins may be formed by power supply pin and ground pin. A control path may avoid a path from the third pin to the fourth pin during both the charging and discharging phases. In addition, the high load may be driven by a programmable driver which uses an amount of current proportionate to the extent of load, thereby avoiding parasitic currents. EMI is further reduced as a result.

Abstract: EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal amount of current, but in opposite direction, is caused to be flown in another pin (“third pin”) located close to the load pin. As a result, the EMI caused by the third pin cancels the EMI generated by the load pin. During a discharge phase, a fourth pin carries and equal amount of current, but in opposite direction, to that in the load pin. The third and fourth pins may be formed by power supply pin and ground pin. A control path may avoid a path from the third pin to the fourth pin during both the charging and discharging phases. In addition, the high load may be driven by a programmable driver which uses an amount of current proportionate to the extent of load, thereby avoiding parasitic currents. EMI is further reduced as a result.

Abstract: An analog or continuous tuning loop which generates an analog signal representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to other such trans-conductor circuits used in a filter) and a reference circuit. The analog signal is used to adjust the trans-conductance such that the current generated by the trans-conductance circuit equals a reference current generated by the reference circuit. A filter using such trans-conductor circuits may be designed to be tuned to a desired cut-off frequency when the desired trans-conductance is achieved. An additional digital circuit generates a few digital bits, which may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter.

Abstract: A digital delay interpolator adapted to receive a first clock signal and a second clock signal, the second clock signal having a transition at a time that is delayed with respect to the time of a transition of the first clock signal, and to provide an output clock signal having a transition at a time intermediate the time of the transition of the first clock signal and the time of the transition of the second clock signal. The interpolator includes a first plurality of selectively enabled delay circuits and a second plurality of selectively enabled delay circuits, the first plurality of delay circuits having an input port being adapted to receive the first clock signal, and the second plurality of delay circuits having an input port being adapted to receive the second clock signal. The first plurality of delay circuits and the second plurality of delay circuits have outputs connected together to form the output of the digital delay interpolator.

Abstract: A digital delay interpolator adapted to receive a first clock signal and a second clock signal, the second clock signal having a transition at a time that is delayed with respect to the time of a transition of the first clock signal, and to provide an output clock signal having a transition at a time intermediate the time of the transition of the first clock signal and the time of the transition of the second clock signal. The interpolator includes a first plurality of selectively enabled delay circuits and a second plurality of selectively enabled delay circuits, the first plurality of delay circuits having an input port being adapted to receive the first clock signal, and the second plurality of delay circuits having an input port being adapted to receive the second clock signal. The first plurality of delay circuits and the second plurality of delay circuits have outputs connected together to form the output of the digital delay interpolator.

Abstract: A data converter (20) comprising an input (I.sub.0 '-I.sub.3 ') for receiving a digital word and an output (V.sub.OUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0'-BL3') formed with an alignment in a first dimension and a plurality of word lines formed (WL0'-WL3') with an alignment in a second dimension different than the first dimension. Still further, the data converter comprises a string (12') comprising a plurality of series connected resistive elements (R10-R24) and a plurality of voltage taps (T10-T25), where at least a majority of the plurality of series connected resistive elements are formed with an alignment in the second dimension. Lastly, the data converter comprises a plurality of switching transistors (ST10-ST25) coupled between the plurality of voltage taps and the output.