Patents by Inventor Debapriya Sahu
Debapriya Sahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11303284Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.Type: GrantFiled: July 14, 2021Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rittu Sachdev
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Publication number: 20220069834Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Debapriya SAHU, Pranav SINHA, Meghna AGRAWAL
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Patent number: 11206051Abstract: A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.Type: GrantFiled: June 9, 2020Date of Patent: December 21, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Srinivas Venkata Veeramreddi, Raghu Ganesan
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Publication number: 20210314018Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.Type: ApplicationFiled: June 16, 2021Publication date: October 7, 2021Inventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
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Patent number: 11095293Abstract: An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.Type: GrantFiled: December 31, 2020Date of Patent: August 17, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rittu Sachdev
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Patent number: 11070242Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.Type: GrantFiled: May 6, 2019Date of Patent: July 20, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
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Publication number: 20210135675Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: ApplicationFiled: January 12, 2021Publication date: May 6, 2021Inventors: Debapriya SAHU, Rittu SACHDEV
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Patent number: 10924123Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: GrantFiled: December 13, 2018Date of Patent: February 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Rittu Sachdev
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Publication number: 20200358472Abstract: A wireless transceiver. The transceiver includes: (i) a transmit signal path; (ii) a calibration path, comprising a conductor to connect a calibration tone into the transmit signal path; (iii) a receive signal path, comprising a first data signal path to process a first data and a second data signal path, different than the first data signal path, to process a second data; (iv) a first capacitive coupling to couple a response to the calibration tone from the transmit signal path to the first data signal path; and (v) a second capacitive coupling to couple a response to the calibration tone from the transmit signal path to the second data signal path.Type: ApplicationFiled: May 6, 2019Publication date: November 12, 2020Inventors: Debapriya Sahu, Rohit Chatterjee, Srinivas Venkata Veeramreddi
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Publication number: 20200304161Abstract: A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.Type: ApplicationFiled: June 9, 2020Publication date: September 24, 2020Inventors: DEBAPRIYA SAHU, SRINIVAS VENKATA VEERAMREDDI, RAGHU GANESAN
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Patent number: 10715194Abstract: A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.Type: GrantFiled: December 29, 2017Date of Patent: July 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Debapriya Sahu, Srinivas Venkata Veeramreddi, Raghu Ganesan
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Publication number: 20200195257Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Inventors: Debapriya SAHU, Rittu SACHDEV
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Publication number: 20190207635Abstract: A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: DEBAPRIYA SAHU, SRINIVAS VENKATA VEERAMREDDI, RAGHU GANESAN
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Publication number: 20190207560Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.Type: ApplicationFiled: November 5, 2018Publication date: July 4, 2019Inventors: Debapriya Sahu, Rohit Chatterjee
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Patent number: 9509323Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.Type: GrantFiled: May 12, 2015Date of Patent: November 29, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishnaswamy Thiagarajan, Jagdish Chand Goyal, Srikanth Manian, Debapriya Sahu
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Publication number: 20150326236Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.Type: ApplicationFiled: May 12, 2015Publication date: November 12, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishnaswamy THIAGARAJAN, Jagdish Chand GOYAL, Srikanth MANIAN, Debapriya SAHU
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Patent number: 8345811Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.Type: GrantFiled: April 2, 2008Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Sarma S. Gunturi, Jawaharlal Tangudu, Sthanunathan Ramakrishnan, Jayawardan Janardhanan, Debapriya Sahu, Subhashish Mukherjee
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Patent number: 8143955Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.Type: GrantFiled: February 4, 2010Date of Patent: March 27, 2012Assignee: Texas Instruments IncorporatedInventors: Gireesh Rajendran, Debapriya Sahu, Alok Prakash Joshi, Ashish Lachhwani
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Publication number: 20110187463Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.Type: ApplicationFiled: February 4, 2010Publication date: August 4, 2011Applicant: Texas Instruments IncorporatedInventors: Gireesh Rajendran, Debapriya Sahu, Alok Prakash Joshi, Ashish Lachwani
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Publication number: 20110171994Abstract: Multi-mode transceiver and a circuit for operating the multi-mode transceiver. A multi-mode transceiver includes a first circuit that is configurable to operate as one of a transmitter and a receiver in a first mode, and a second circuit that is configurable to operate as one of the transmitter and the receiver in a second mode. The multi-mode transceiver includes a first element coupled to the first circuit. The multi-mode transceiver includes a second element coupled to the first element and one or more ports. The multi-mode transceiver also includes a first switch, coupled to the second element and to the second circuit, that is configurable to operate the transceiver in at least one of the first mode and the second mode in conjunction with the first element and the second element.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: Texas Instruments IncorporatedInventors: Gireesh RAJENDRAN, Timothy Don DAVIS, Apu SIVADAS, Michel FRECHETTE, Thiagarajan KRISHNASWAMY, Salvatore PENNISI, Rakesh KUMAR, Bijit Thakorbhai PATEL, Subhashish MUKHERJEE, Debapriya SAHU