Abstract: Embodiments of the present disclosure relate to methods for in-situ deposition and treatment of a thin film for improved step coverage. In one embodiment, the method for processing a substrate is provided. The method includes forming a dielectric layer on patterned features of the substrate by exposing the substrate to a gas mixture of a first precursor and a second precursor simultaneously with plasma present in a process chamber, wherein the plasma is formed by a first pulsed RF power, exposing the dielectric layer to a first plasma treatment using a gas mixture of nitrogen and helium in the process chamber, and performing a plasma etch process by exposing the dielectric layer to a plasma formed from a gas mixture of a fluorine-containing precursor and a carrier gas, wherein the plasma is formed in the process chamber by a second pulsed RF power.

Abstract: Exemplary semiconductor processing chambers may include a showerhead. The chambers may also include a substrate support characterized by a first surface facing the showerhead. The first surface may be configured to support a semiconductor substrate. The substrate support may define a recessed pocket centrally located within the first surface. The recessed pocket may be defined by an outer radial wall characterized by a height from the first surface within the recessed pocket that is greater than or about 150% of a thickness of the semiconductor substrate.

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

Abstract: A method of forming a low-k dielectric layer with barrier properties is disclosed. The method comprises forming a dielectric layer by PECVD which is doped with one or more of boron, nitrogen or phosphorous. The dopant gas of some embodiments may be coflowed with the other reactants during deposition.

Abstract: In one implementation, a method comprising depositing one or more silicon oxide/silicon nitride containing stacks on a substrate positioned in a processing chamber is provided. Depositing the one or more silicon oxide/silicon nitride containing stacks comprises (a) energizing a first process gas into a first plasma, (b) depositing a first film layer over the substrate from the first plasma, (c) energizing a second process gas into a second plasma, wherein the second process gas comprises a compound having at least one silicon-nitrogen bond and (d) depositing a second film layer on the first film layer from the second plasma. The method further comprises repeating (a), (b), (c), and (d) until a predetermined number of first film layers and second film layers have been deposited on the substrate. The first film layer is a silicon oxide layer and the second film layer is a silicon nitride layer.

Abstract: A method of depositing a coating and a layered structure is provided. A coating is deposited on a substrate to make a layered structure, such that an interface between the coating and the substrate is formed. The coating includes silicon, oxygen, and carbon, where the carbon doping in the coating increases between the interface and the top surface of the coating. The top surface of the coating is inherently hydrophobic and icephobic, and reduces the wetting of water or ice film on the layered structure, without requiring reapplication of the coating.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: Embodiments described herein relate to gas line systems with a multichannel splitter spool. In these embodiments, the gas line systems will include a first gas line that is configured to supply a first gas. The first gas line is coupled to a multichannel splitter spool with a plurality of second gas lines into which the first gas flows. Each gas line of the plurality of second gas lines will have a smaller volume than the volume of the first gas line. The smaller second gas lines will be wrapped by a heater jacket. Due to the smaller volume of the second gas lines, when the first gas is flowed through the second gas lines, the heater jacket will sufficiently heat the first gas, eliminating the condensation induced particle defects that occur in conventional gas line systems when the first gas meets with a second gas in the gas line system.

Abstract: A method of forming a film stack with reduced defects is provided and includes positioning a substrate on a substrate support within a processing chamber and sequentially depositing polysilicon layers and silicon oxide layers to produce the film stack on the substrate. The method also includes supplying a current of greater than 5 ampere (A) to a plasma profile modulator while generating a deposition plasma within the processing chamber, exposing the substrate to the deposition plasma while depositing the polysilicon layers and the silicon oxide layers, and maintaining the processing chamber at a pressure of greater than 2 Torr to about 100 Torr while depositing the polysilicon layers and the silicon oxide layers.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: Methods for forming the silicon boron nitride layer are provided. The method includes positioning a substrate on a pedestal in a process region within a process chamber, heating a pedestal retaining the substrate, and introducing a first flow of a first process gas and a second flow of a second process gas to the process region. The first flow of the first process gas contains silane, ammonia, helium, nitrogen, argon, and hydrogen. The second flow of the second process gas contains diborane and hydrogen. The method also includes forming a plasma concurrently with the first flow of the first process gas and the second flow of the second process gas to the process region and exposing the substrate to the first process gas, the second process gas, and the plasma to deposit the silicon boron nitride layer on the substrate.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.

Abstract: Methods for depositing hardmask materials and films, and more specifically, for depositing phosphorus-doped, silicon nitride films are provided. A method of depositing a material on a substrate in a processing chamber includes exposing a substrate to a deposition gas in the presence of RF power to deposit a phosphorus-doped, silicon nitride film on the substrate during a plasma-enhanced chemical vapor deposition (PE-CVD) process. The deposition gas contains one or more silicon precursors, one or more nitrogen precursors, one or more phosphorus precursors, and one or more carrier gases. The phosphorus-doped, silicon nitride film has a phosphorus concentration in a range from about 0.1 atomic percent (at %) to about 10 at %.

Abstract: Embodiments of the disclosure describe an apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes. In one example, a method includes positioning a substrate on a substrate support in a process chamber, and flowing a deposition gas mixture comprising a silicon containing gas and a reacting gas to the process chamber through a showerhead having a convex surface facing the substrate support or a concave surface facing the substrate support in accordance with a stress profile of the substrate. A plasma is formed in the presence of the deposition gas mixture in the process chamber by applying an RF power to multiple coupling points of the showerhead that are symmetrically arranged about a center point of the showerhead. A deposition process is then performed on the substrate.

Abstract: Embodiments disclosed herein include methods of forming high quality silicon nitride films. In an embodiment, a method of depositing a film on a substrate may comprise forming a silicon nitride film over a surface of the substrate in a first processing volume with a deposition process, and treating the silicon nitride film in a second processing volume, wherein treating the silicon nitride film comprises exposing the film to a plasma induced by a modular high-frequency plasma source. In an embodiment, a sheath potential of the plasma is less than 100 V, and a power density of the high-frequency plasma source is approximately 5 W/cm2 or greater, approximately 10 W/cm2 or greater, or approximately 20 W/cm2 or greater.

Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1?x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

Abstract: Embodiments disclosed herein generally relate to systems and methods to prevent free radical damage to sensitive components in a process chamber and optimizing flow profiles. The processing chamber utilizes a cover substrate on lift pins and an inert bottom purge flow to shield the substrate support from halogen reactants. During a clean process, the cover substrate and the purge flow restricts halogen reactants from contacting the substrate support. The method of cleaning includes placing a cover substrate on a plurality of lift pins that extend through a substrate support in a processing chamber, raising the cover substrate via the lift pins to expose a space between the cover substrate and the substrate support, supplying a halogen containing gas into the processing chamber, supplying a second gas through an opening in the processing chamber, and flowing the second gas through the space between the cover substrate and the substrate support.

Abstract: Implementations of the present disclosure provide methods for processing substrates in a processing chamber. In one implementation, the method includes (a) depositing a dielectric layer on a first substrate at a first chamber pressure using a first high-frequency RF power, (b) depositing sequentially a dielectric layer on N substrates subsequent to the first substrate at a second chamber pressure, wherein N is an integral number of 5 to 10, and wherein depositing each substrate of N substrates comprises using a second high-frequency RF power that has a power density of about 0.21 W/cm2 to about 0.35 W/cm2 lower than that of the first high-frequency RF power, (c) performing a chamber cleaning process without the presence of a substrate, and (d) repeating (a) to (c).