Abstract: Aspects disclosed herein relate to methods of depositing pure silicon oxide on a substrate using Octamethylcyclotetrasiloxane (OMCTS) precursor. In one aspect, the method generally includes positioning a substrate in a processing chamber, introducing an oxygen-containing gas into the processing chamber, introducing OMCTS precursor into the processing chamber, and reacting the oxygen-containing gas and the OMCTS precursor to remove carbon and deposit pure silicon oxide on the substrate.

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon (a-Si) layers on a semiconductor substrate. In one implementation, a method is provided. The method comprises generating a pressure within a processing volume between 2 Torr and 60 Torr. The method further comprises heating a substrate in the processing volume to a temperature between 300 degrees Celsius and 550 degrees Celsius. The method further comprises flowing a silane-containing gas mixture into the processing volume having the substrate positioned therein. The method further comprises flowing a borane-containing gas mixture into the processing volume having the substrate positioned therein and depositing a boron-doped amorphous silicon layer on the substrate.

Abstract: Embodiments described herein provide a method of forming a low-k carbon-doped silicon oxide (CDO) layer having a high hardness by a plasma-enhanced chemical vapor deposition (PECVD) process. The method includes providing a carrier gas at a carrier gas flow rate and a CDO precursor at a precursor flow rate to a process chamber. A radio frequency (RF) power is applied at a power level and a frequency to the CDO precursor. The CDO layer is deposited on a substrate within the process chamber.

Abstract: Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

Abstract: Embodiments described herein relate to methods of forming silicon nitride films. In one embodiment, a first process gas set including a silicon-containing gas and a first nitrogen-containing gas is flowed into the process chamber. An initiation layer is deposited by applying a first radio frequency power to the first process gas set at a first frequency and a first power level. The first flow of the first nitrogen-containing gas of the first process gas set is discontinued and a second process gas set including the silicon-containing gas, a second nitrogen-containing gas, and a hydrogen-containing gas is flowed into the process chamber. A bulk silicon nitride layer is deposited on the initiation layer by applying a second RF power to the second process gas set at a second frequency higher than the first frequency and a second power level higher than the first power level.

Abstract: Embodiments of the present disclosure relate to methods for in-situ deposition and treatment of a thin film for improved step coverage. In one embodiment, the method for processing a substrate is provided. The method includes forming a dielectric layer on patterned features of the substrate by exposing the substrate to a gas mixture of a first precursor and a second precursor simultaneously with plasma present in a process chamber, wherein the plasma is formed by a first pulsed RF power, exposing the dielectric layer to a first plasma treatment using a gas mixture of nitrogen and helium in the process chamber, and performing a plasma etch process by exposing the dielectric layer to a plasma formed from a gas mixture of a fluorine-containing precursor and a carrier gas, wherein the plasma is formed in the process chamber by a second pulsed RF power.

Abstract: Embodiments disclosed herein relate to methods for forming memory devices, and more specifically to improved methods for forming a dielectric encapsulation layer over a memory material in a memory device. In one embodiment, the method includes thermally depositing a first material over a memory material at a temperature less than the temperature of the thermal budget of the memory material, exposing the first material to nitrogen plasma to incorporate nitrogen in the first material, and repeating the thermal deposition and nitrogen plasma operations to form a hermetic, conformal dielectric encapsulation layer over the memory material. Thus, a memory device having a hermetic, conformal dielectric encapsulation layer over the memory material is formed.

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided.

Abstract: Embodiments of the invention contemplate a shadow ring that provides increased or decreased and more uniform deposition on the edge of a wafer. By removing material from the top and/or bottom surfaces of the shadow ring, increased edge deposition and bevel coverage can be realized. In one embodiment, the material on the bottom surface is reduced by providing a recessed slot on the bottom surface. By increasing the amount of material of the shadow ring, the edge deposition and bevel coverage is reduced. Another approach to adjusting the deposition at the edge of the wafer includes increasing or decreasing the inner diameter of the shadow ring. The material forming the shadow ring may also be varied to change the amount of deposition at the edge of the wafer.

Abstract: Embodiments described herein relate to methods of forming silicon nitride films. In one embodiment, a first process gas set including a silicon-containing gas and a first nitrogen-containing gas is flowed into the process chamber. An initiation layer is deposited by applying a first radio frequency power to the first process gas set at a first frequency and a first power level. The first flow of the first nitrogen-containing gas of the first process gas set is discontinued and a second process gas set including the silicon-containing gas, a second nitrogen-containing gas, and a hydrogen-containing gas is flowed into the process chamber. A bulk silicon nitride layer is deposited on the initiation layer by applying a second RF power to the second process gas set at a second frequency higher than the first frequency and a second power level higher than the first power level.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.

Abstract: Embodiments of the invention contemplate a shadow ring that provides increased or decreased and more uniform deposition on the edge of a wafer. By removing material from the top and/or bottom surfaces of the shadow ring, increased edge deposition and bevel coverage can be realized. In one embodiment, the material on the bottom surface is reduced by providing a recessed slot on the bottom surface. By increasing the amount of material of the shadow ring, the edge deposition and bevel coverage is reduced. Another approach to adjusting the deposition at the edge of the wafer includes increasing or decreasing the inner diameter of the shadow ring. The material forming the shadow ring may also be varied to change the amount of deposition at the edge of the wafer.

Abstract: Aspects disclosed herein relate to methods of depositing pure silicon oxide on a substrate using Octamethylcyclotetrasiloxane (OMCTS) precursor. In one aspect, the method generally includes positioning a substrate in a processing chamber, introducing an oxygen-containing gas into the processing chamber, introducing OMCTS precursor into the processing chamber, and reacting the oxygen-containing gas and the OMCTS precursor to remove carbon and deposit pure silicon oxide on the substrate.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon (a-Si) layers on a semiconductor substrate. In one implementation, a method is provided. The method comprises generating a pressure within a processing volume between 2 Torr and 60 Torr. The method further comprises heating a substrate in the processing volume to a temperature between 300 degrees Celsius and 550 degrees Celsius. The method further comprises flowing a silane-containing gas mixture into the processing volume having the substrate positioned therein. The method further comprises flowing a borane-containing gas mixture into the processing volume having the substrate positioned therein and depositing a boron-doped amorphous silicon layer on the substrate.

Abstract: Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract: Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer (SAM) is selectively formed on the exposed metal surface and prevents or discourages formation of poreseal on the metal. The SAM is selectively formed by exposing a patterned substrate to a SAM molecule which preferentially binds to exposed metal surfaces rather than exposed dielectric surfaces. The selected SAM molecules tend to not bind to low-k films. The SAM and SAM molecule are also chosen so the SAM tolerates subsequent processing at relatively high processing temperatures above 140° C. or 160° C. Aliphatic or aromatic SAM molecules with thiol head moieties may be used to form the SAM.