Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Abstract: A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: A controllable resistive element and method for updating the resistance of the same includes a state device configured to provide a voltage-controlled resistance responsive to a voltage input. A battery is configured to apply a voltage to the voltage input of the state device based on a charge stored in the battery. A write device is configured to charge the battery responsive to a write signal. An erase device is configured to discharge the battery responsive to an erase signal.

Abstract: A method for updating the resistance of a controllable resistance element includes determining an amount of resistance change for the controllable resistive element. A charge difference for a battery is determined corresponding to the resistance change for the controllable resistive element. The battery is charged or discharged to effect the resistance change in the controllable resistive element.

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.

Abstract: An argmax circuit includes input nodes coupled to a first set of comparators to receive a plurality of analog input signals each associated with a channel number, the first set of comparators outputting a plurality of first analog results and input nodes coupled to a second set of comparators to receive and process the plurality of first analog results, the second set of comparators outputting a plurality of second analog results processed by additional comparators in a cascading manner in a forward direction until a single comparator remains with a single output. A plurality of comparators including the first set, the second set, and the additional comparators are executed in a reverse direction to determine the channel number from which the single output originated from.

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.