Patents by Inventor Digvijay A. Raorane
Digvijay A. Raorane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128162Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Inventors: Ravindranath MAHAJAN, Debendra MALLIK, Sujit SHARAN, Digvijay RAORANE
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Publication number: 20230411245Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.Type: ApplicationFiled: August 28, 2023Publication date: December 21, 2023Inventors: Ravindranath MAHAJAN, Debendra MALLIK, Sujit SHARAN, Digvijay RAORANE
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Publication number: 20230360994Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicant: Intel CorporationInventors: Debendra MALLIK, Ravindranath MAHAJAN, Digvijay RAORANE
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Patent number: 11798865Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.Type: GrantFiled: March 4, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Ravindranath Mahajan, Debendra Mallik, Sujit Sharan, Digvijay Raorane
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Patent number: 11749577Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: GrantFiled: December 27, 2022Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
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Patent number: 11742270Abstract: An apparatus is provided which comprises: a plurality of interconnects to couple a silicon interposer to a substrate; and a landing pad configured in a non-circle shape, wherein the plurality of interconnects are adjacent to the landing pad at one end of the plurality of interconnects through a plurality of vias.Type: GrantFiled: December 15, 2016Date of Patent: August 29, 2023Assignee: Intel CorporationInventor: Digvijay A. Raorane
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Patent number: 11742261Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.Type: GrantFiled: December 27, 2022Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Ravindranath Mahajan, Debendra Mallik, Sujit Sharan, Digvijay Raorane
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Publication number: 20230197636Abstract: An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.Type: ApplicationFiled: February 21, 2023Publication date: June 22, 2023Applicant: Intel CorporationInventors: Debendra MALLIK, Digvijay A. RAORANE
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Publication number: 20230197574Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: ApplicationFiled: February 17, 2023Publication date: June 22, 2023Inventors: Aditya S. VAIDYA, Ravindranath V. MAHAJAN, Digvijay A. RAORANE, Paul R. START
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Publication number: 20230138386Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.Type: ApplicationFiled: December 20, 2022Publication date: May 4, 2023Applicant: Intel CorporationInventors: ANDREW P. COLLINS, DIGVIJAY A. RAORANE, WILFRED GOMES, RAVINDRANATH V. MAHAJAN, SUJIT SHARAN
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Publication number: 20230133429Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.Type: ApplicationFiled: December 27, 2022Publication date: May 4, 2023Inventors: Ravindranath MAHAJAN, Debendra MALLIK, Sujit SHARAN, Digvijay RAORANE
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Publication number: 20230132197Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: ApplicationFiled: December 27, 2022Publication date: April 27, 2023Applicant: Intel CorporationInventors: Debendra MALLIK, Ravindranath MAHAJAN, Digvijay RAORANE
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Publication number: 20230108000Abstract: An integrated circuit structure comprises one or more first level interconnects (FLIs) embedded in an underfill (UF) over a substrate. An etch stop layer is over the FLIs. A passivation layer is over the etch stop layer and a plurality of vias are through the passivation layer. A plurality of contacts are on the passivation layer in contact with the vias to connect with the FLI. A plurality of topological crack stop (TCS) features are formed in the passivation layer and on a top surface of the etch stop layer.Type: ApplicationFiled: September 24, 2021Publication date: April 6, 2023Inventors: Vishal JAVVAJI, Christopher M. PELTO, Dimitrios ANTARTIS, Digvijay A. RAORANE, Michael P. O'DAY, Seung-June CHOI
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Patent number: 11587851Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: GrantFiled: May 18, 2021Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Patent number: 11581235Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: GrantFiled: April 19, 2021Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
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Patent number: 11569173Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.Type: GrantFiled: December 29, 2017Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Andrew P. Collins, Digvijay A. Raorane, Wilfred Gomes, Ravindranath V. Mahajan, Sujit Sharan
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Patent number: 11527489Abstract: An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.Type: GrantFiled: June 29, 2018Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Michael J. Hill, Mathew Manusharow, Beomseok Choi, Digvijay Raorane
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Publication number: 20220352121Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.Type: ApplicationFiled: July 5, 2022Publication date: November 3, 2022Inventors: Debendra MALLIK, Digvijay A. RAORANE, Ravindranath Vithal MAHAJAN, Mitul Bharat MODI
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Patent number: 11488880Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.Type: GrantFiled: June 30, 2017Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Vijay K. Nair, Digvijay A. Raorane
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Patent number: 11417630Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.Type: GrantFiled: December 29, 2016Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Debendra Mallik, Digvijay A. Raorane, Ravindranath Vithal Mahajan, Mitul Bharat Modi