Patents by Inventor Digvijay A. Raorane
Digvijay A. Raorane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220230972Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Inventors: Digvijay A. RAORANE, Ian En Yoon CHIN, Daniel N. SOBIESKI
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Patent number: 11322457Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.Type: GrantFiled: April 15, 2020Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Digvijay A. Raorane, Ian En Yoon Chin, Daniel N. Sobieski
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Publication number: 20220102242Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
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Publication number: 20220102231Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane
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Patent number: 11239186Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include a substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed on the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.Type: GrantFiled: September 23, 2016Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Digvijay Raorane, Vijay K. Nair
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Patent number: 11189573Abstract: A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.Type: GrantFiled: March 31, 2016Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Vijay K. Nair, Digvijay Raorane
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Patent number: 11145583Abstract: Embodiments include packages substrates and a method of forming the package substrate. A package substrate includes a first dielectric comprising a first conductive layer, and a second dielectric comprising a second conductive layer and a third conductive layer. The second and third conductive layers are embedded in the second dielectric, where a top surface of the third conductive layer is above a top surface of the second conductive layer. The package substrate has a fourth conductive layer on the second dielectric. The first dielectric has a first dielectric thickness between the first and third conductive layers. The first dielectric also has a second dielectric thickness between the first and second conductive layers. The package substrate includes the second dielectric thickness that is greater than the first dielectric thickness. The second dielectric may have a z-height of a first bottom surface greater than a z-height of a second bottom surface.Type: GrantFiled: May 3, 2018Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Digvijay Raorane, Yidnekachew Mekonnen
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Publication number: 20210305132Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Omkar KARHADE, Digvijay RAORANE, Sairam AGRAHARAM, Nitin DESHPANDE, Mitul MODI, Manish DUBEY, Edvin CETEGEN
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Publication number: 20210305133Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads, and an open cavity. A bridge die is in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, a power delivery bridge pad between the first plurality of bridge pads and the second plurality of bridge pads, and conductive traces. A first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads. A second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads. A power delivery conductive line is coupled to the power delivery bridge pad.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Omkar KARHADE, Mitul MODI, Sairam AGRAHARAM, Nitin DESHPANDE, Digvijay RAORANE
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Patent number: 11128029Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.Type: GrantFiled: September 26, 2016Date of Patent: September 21, 2021Assignee: Intel CorporationInventors: Vijay K. Nair, Digvijay Raorane
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Publication number: 20210287975Abstract: An apparatus is provided which comprises: a plurality of interconnects to couple a silicon interposer to a substrate; and a landing pad configured in a non-circle shape, wherein the plurality of interconnects are adjacent to the landing pad at one end of the plurality of interconnects through a plurality of vias.Type: ApplicationFiled: December 15, 2016Publication date: September 16, 2021Applicant: Intel CorporationInventor: Digvijay A. Raorane
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Publication number: 20210272881Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Aditya S. VAIDYA, Ravindranath V. MAHAJAN, Digvijay A. RAORANE, Paul R. START
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Publication number: 20210242104Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Applicant: Intel CorporationInventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
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Patent number: 11049798Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.Type: GrantFiled: June 28, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
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Patent number: 11011448Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: GrantFiled: August 1, 2019Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
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Publication number: 20210057348Abstract: Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.Type: ApplicationFiled: December 19, 2017Publication date: February 25, 2021Inventors: Ehren HWANG, Christopher M. PELTO, Seshu V. SATTIRAJU, Shravan GOWRISHANKAR, Zachary A. ZELL, Digvijay A. RAORANE
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Publication number: 20210035881Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.Type: ApplicationFiled: August 1, 2019Publication date: February 4, 2021Applicant: Intel CorporationInventors: Debendra Mallik, Ravindranath Mahajan, Digvijay Raorane
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Publication number: 20200286814Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.Type: ApplicationFiled: March 4, 2019Publication date: September 10, 2020Inventors: Ravindranath MAHAJAN, Debendra MALLIK, Sujit SHARAN, Digvijay RAORANE
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Publication number: 20200251426Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.Type: ApplicationFiled: April 15, 2020Publication date: August 6, 2020Inventors: Digvijay A. RAORANE, Ian En Yoon CHIN, Daniel N. SOBIESKI
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Publication number: 20200098655Abstract: Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.Type: ApplicationFiled: June 30, 2017Publication date: March 26, 2020Applicant: Intel CorporationInventors: Vijay K. Nair, Digvijay A. Raorane