Abstract: The socket releasably couples a packaged integrated circuit to a circuit board. The socket includes a clamp, a latch, and an array interconnect. The clamp is configured to be pivotally coupled to a circuit board. The latch is configured to be coupled to the circuit board and configured to releasably hold the clamp in a predetermined position. The array interconnect configured to be coupled to the printed circuit board. In use the latch releasably holds the hinged clamp in the predetermined position to clamp both a packaged integrated circuit between the clamp and the array interconnect, and the array interconnect between the packaged integrated circuit and the circuit board.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.

Abstract: A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.

Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Abstract: Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Abstract: A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A master-slave system includes a clock and phase signal generator to produce a clock signal at a given frequency and a phase signal at an effective frequency, where the phase signal may or may not be periodic and has an effective frequency less than the given frequency. A clock line is connected to the clock and phase signal generator to carry the clock signal. A phase line is connected to the clock and phase signal generator to carry the phase signal. The phase line includes a phase-to-master path to carry a phase-to-master phase signal and a phase-from-master path to carry a phase-from-master phase signal. A master device is connected to the clock line and the phase line. A data bus is connected to the master device. A slave device is connected to the data bus, the clock line and the phase line. The slave device processes data on the data bus in response to the clock signal and the phase signal.

Abstract: An RF object locating system and method that uses or includes a set of N (N>2) receivers (monitoring stations) located at fixed positions in and/or about a region to be monitored, one or more reference transmitters that transmit a timing reference, a location processor that determines object location based on time-of-arrival measurements, and at least one object having an untethered tag transmitter that transmits RF pulses, which may additionally include object ID or other information. Free-running counters in the monitoring stations, whose phase offsets are determined relative to a reference transmitter, are frequency-locked with a centralized reference clock. Time-of-arrival measurements made at the monitoring stations may be stored and held in a local memory until polled by the location processor.

Abstract: An integrated circuit memory device that include an input receiver, an output driver, and a capacitive coupling element. The capacitive coupling element includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the input receiver and the output driver, an the second capacitor electrode couples to an external signal line. Delay modulated data is received by the input receiver from the external signal line via the capacitive coupling element.

Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative to one another so as to provide a predetermined electrical impedance and may be arranged to carry electrical signals as transmission lines. A dielectric spacer (36) may be disposed between the first and second bus conductors to provide the spacing. Contact regions (24) of the first and second conductors (22a, 22b) may provide compliant coupling regions for the socket (14). The contact regions (24) of the first bus conductor (22a) may be positioned within the socket (14) so as to contact a lead disposed on a first side of a circuit element (16) and the contact regions (24) of the second bus conductor (22b) may be positioned within the socket (14) so as to contact the lead disposed on the second side of the circuit element (16).

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.