Abstract: An RF object locating system and method that uses or includes a set of N (N>2) receivers (monitoring stations) located at fixed positions in and/or about a region to be monitored, one or more reference transmitters that transmit a timing reference, a location processor that determines object location based on time-of-arrival measurements, and at least one object having an untethered tag transmitter that transmits RF pulses, which may additionally include object ID or other information. Free-running counters in the monitoring stations, whose phase offsets are determined relative to a reference transmitter, are frequency-locked with a centralized reference clock. Time-of-arrival measurements made at the monitoring stations may be stored and held in a local memory until polled by the location processor.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.

Abstract: A clock signal desired to be transmitted to various components of the electronic system is combined with a noise signal to generate a spread spectrum clock signal which, in turn, is distributed with an associated reference signal to selected components of the system using two-channel communication links. A receiving circuit within each of the selected components recovers the original clock signal from the spread spectrum clock signal and its associated reference signal. In one embodiment, the clock signal is combined with the noise signal in an exclusive-OR logic gate to generate a spread spectrum clock signal which is distributed to receiving components using a first channel. The noise signal is transmitted as the reference signal using the second channel. The two channel signals are combined in an exclusive-OR gate of one or more receiving circuits to recover the clock signal.

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract: A circuit to control the edge rate of a digital signal includes a conductor to carry a digital signal. A first capacitive component has a first node and a second node, with the second node being coupled to the conductor. A first phase control circuit has a first input node coupled to the conductor, a second input node to receive a first enable signal and an output node coupled to the first node of the first capacitive component. The first phase control circuit processes the digital signal from the conductor and the first enable signal to produce a control signal at the output node to control the edge rate of the digital signal. The first phase control circuit produces the control signal in one of at least two different phase relationships with the digital signal according to a state of the first enable signal. The control signal may be in phase with the digital signal or complementary to the digital signal.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.

Abstract: An electronic device includes a standard dielectric material and a lossy material integrated with the standard dielectric material to selectively control the distributed resistance of the standard dielectric material. The lossy material may be inserted into the standard dielectric material. The inserted material may be resistive particles, carbon particles, open cell conductive foam, carbon impregnated open cell conductive foam, and the like. The lossy material may also be a loss inducing physical structure attached to the standard dielectric material. The loss inducing physical structure may be a planar resistive layer attached to the standard dielectric material. The planar resistive layer may have an extended surface to attenuate high frequency signals.

Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract: Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.

Abstract: A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract: A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.