Abstract: An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

Abstract: The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

Abstract: A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

Abstract: The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

Abstract: A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

Abstract: A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

Abstract: An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes, a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuits and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated white the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

Abstract: A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.

Abstract: A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.

Abstract: A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

Abstract: A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: A solution for allowing conditional access to IP-based broadcast services in a passive optical network is disclosed. When a subscriber requests broadcast services by selecting a broadcast channel, an IP set-top converts the request into an IGMP join message and forwards the message to an ONU/ONT, a unit on the subscriber's side. The ONU/ONT delivers the message to an OLT interworking with a router while storing mapping information of the port that received the message and a MAC address of the selected channel. Thereafter, the OLT extracts information on MAC address of the IP set-top box and the requested broadcast data. The OLT compares the extracted information to the subscriber's subscription information and determines whether to provide the requested broadcast services. If the broadcast services may be provided, the broadcast data provided from the broadcast server is transmitted to the IP set-top box via ONU/ONT based on the stored mapping information.

Abstract: A network packet generation apparatus and method with an attack test packet generation function for testing a performance of an information security system is provided. The network packet generation method includes the steps of: setting attack test packets according to setting data inputted by a user and a pre-stored attack detection rule; generating the attack test packets according to the setting data; transmitting the attack test packets to the information security system and receiving monitored and stored reaction packets against the attack test packets; and analyzing the received reaction packets, thereby making it possible to improve the accuracy and reliability of an information security system test and reduce the necessary time for the information security system test.

Abstract: A method for analyzing a security grade of an information property, and more particularly, a method by which a security grade (a risk degree in security) is analyzed objectively and quantitatively such that risk degree management of an information property can be efficiently performed, is provided. The method for analyzing a security grade of an information property includes: selecting an information property as an object of security grade analysis, among information properties for which risk degree analysis and importance evaluation in managerial, physical, and technological aspects are performed; calculating the property risk degree of the selected property based on the weighted mean of risk degrees and importance evaluation; and mapping the weighted mean of the risk degree and the importance on a 2-dimensional plane having the X-axis indicating the weighted mean of a risk degree and the Y-axis indicating importance, and based on the appearing result, determining the priority of a safeguard.

Abstract: The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

Abstract: A system and method for managing link status in Gigabit Ethernet passive optical network (GE-PON) units (ONUs) is disclosed. The GE-PON comprises one or more ONUs allocated data transmission periods, respectively. Each of the ONUs sends a report signal and a data signal in a corresponding one of the allocated data transmission periods. The report signal contains a signal to request allocation of a bandwidth for data signal transmission in a next window period. The GE-PON further comprises an optical splitter having its one side connected with the ONUs and its other side connected with at least one optical communication channel. The optical splitter switches an input signal to a desired destination.

Abstract: A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.