Abstract: The present invention provides a steering apparatus for a vehicle, the apparatus including: a plate bracket supported on distance brackets and having a first slot through which an adjustment bolt passes, the distance brackets being coupled to the outer circumferential surface of an upper tube to face each other; a stationary gear coupled to the plate bracket, wherein the stationary gear has a second slot that corresponds to the first slot and through which the adjustment bolt passes and first gear teeth formed at opposite edges thereof; and a movable gear having a through-hole through which adjustment bolt passes and second gear teeth formed on opposite sides thereof and engaged with the first gear teeth.

Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.

Abstract: A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time.

Abstract: A circuit board for a power supply, an electronic apparatus including the same, and an inductor device are provided. The circuit board includes a first pattern arranged on a first layer of the circuit board and including a first terminal coupled to a coil, a first layer region arranged on the first layer, the coil being disposed on the first layer region, and a second pattern arranged on a second layer of the circuit board, below the first layer. The second pattern includes a first blank region located below the first layer region, and has no conductive material arranged thereon.

Abstract: An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.

Abstract: An electronic device comprising a semiconductor memory unit that may include a cell array including a plurality of storage cells; a first line connected to one ends of the plurality of storage cells; a second line connected to the other ends of the plurality of storage cells; a first driver connected to one end of the first line at a first contact location on one side of the cell array, and configured to apply a first electrical signal to the one end of the first line; and a second driver connected to one end of the second line at a second contact location on a side of the cell array opposing the side of the cell array where the first contact location is located, and configured to apply a second electrical signal to the one end of the second line.

Abstract: A memory device may include: first to Nth cell blocks; first to (N?1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block.

Abstract: According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.

Abstract: An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.

Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to

Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

Abstract: A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time.

Abstract: An electronic device comprising a semiconductor memory unit that may include a cell array including a plurality of storage cells; a first line connected to one ends of the plurality of storage cells; a second line connected to the other ends of the plurality of storage cells; a first driver connected to one end of the first line at a first contact location on one side of the cell array, and configured to apply a first electrical signal to the one end of the first line; and a second driver connected to one end of the second line at a second contact location on a side of the cell array opposing the side of the cell array where the first contact location is located, and configured to apply a second electrical signal to the one end of the second line.

Abstract: In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.

Abstract: A memory device may include: first to Nth cell blocks; first to (N?1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block.

Abstract: A data sense amplifier may include: first and second external nodes, wherein a potential difference occurs between the first and second external nodes when a memory cell is selected; an amplification unit suitable for generating and amplifying a potential difference between first and second nodes in response to the potential difference between the first and second external nodes; and a switching unit suitable for electrically coupling the first and second external nodes to the first and second nodes, respectively, after a predetermined time elapses from when the memory cell is selected.

Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to

Abstract: According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.