Abstract: Embodiments of the disclosure generally relate to a layer stack containing a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. The layer stack includes a channel layer containing an amorphous silicon layer disposed on a substrate and a gate insulating layer disposed on the channel layer. The gate insulating layer contains a silicon dioxide layer disposed on the channel layer, a zirconium dioxide layer disposed on the silicon dioxide layer, and an interface layer disposed on the zirconium dioxide layer and containing titanium oxide or aluminum oxide. The zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 ? or greater, the gate insulating layer has a K value of about 20 to about 50, and the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

Abstract: Embodiments of the present disclosure generally relate to a layer stack including a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. In one embodiment, the layer stack includes a substrate, a channel layer disposed on the substrate, and a gate insulating layer. The gate insulating layer includes an interface layer disposed on the channel layer and a zirconium dioxide layer disposed on the interface layer. The gate insulating layer has a K value ranging from about 20 to about 50. The high k value of the gate insulating layer reduces the subthreshold swing (SS) causing a higher energy barrier which alleviates the short channel effect and leakage in display devices. Additionally, the high k value of the gate insulating layer enables for a faster driving current that improves brightness and performance of the display device.

Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between a metal electrode layer and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a metal electrode layer disposed on a barrier layer formed above a gate insulating material layer, an interface layer disposed on the metal electrode layer, wherein the interface layer is an oxygen free dielectric material layer sized to be formed predominately on the metal electrode layer, and an insulating material layer disposed on the interface layer, wherein the insulating material layer is an oxygen containing dielectric layer.

Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a substrate-processing chamber. In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material.

Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a substrate-processing chamber. In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual ZrO2 containing film formed on one or more interior surfaces of the processing chamber. The reactive species is formed from BCl3 and the one or more interior surfaces includes at least one exposed Al2O3 surface The method further comprises reacting the residual ZrO2 containing film with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber, wherein a removal rate of the residual ZrO2 containing film is greater than a removal rate of Al2O3.

Abstract: In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO2) and hafnium dioxide (HfO2). The coating material includes a compound selected from alumina (Al2O3), yttrium-containing compounds, and combinations thereof.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Abstract: The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple substrates are disposed on opposite sides of the processing source within the processing chamber, yet the processing environments are not isolated from each other. The processing source is a horizontally centered vertical plasma generator that permits multiple substrates to be processed simultaneously on either side of the plasma generator, yet independent of each other. The system is arranged as a twin system whereby two identical processing lines, each with their own processing chamber, are arranged adjacent to each other. Multiple robots are used to load and unload the substrates from the processing system. Each robot can access both processing lines within the system.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source and drain electrodes are formed, but before the passivation layers or etch stop layers are deposited thereover, the active channel is exposed to an N2O or O2 plasma. The interface between the active channel and the passivation layers or etch stop layers are either altered or damaged during formation of the source and drain electrodes. The N2O or O2 plasma alters and repairs the interface between the active channel and the passivation or etch stop layers.

Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between a metal electrode layer and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a metal electrode layer disposed on a barrier layer formed above a gate insulating material layer, an interface layer disposed on the metal electrode layer, wherein the interface layer is an oxygen free dielectric material layer sized to be formed predominately on the metal electrode layer, and an insulating material layer disposed on the interface layer, wherein the insulating material layer is an oxygen containing dielectric layer.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure includes source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10, and a gate electrode formed above or below the gate insulating layer.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.