Patents by Inventor Dong-Kil Yim
Dong-Kil Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8372205Abstract: A substrate support and method for fabricating the same are provided. In one embodiment of the invention, a substrate support includes an electrically conductive body having a substrate support surface that is covered by an electrically insulative coating. At least a portion of the coating centered on the substrate support surface has a surface finish of between about 200 to about 2000 micro-inches. In another embodiment, a substrate support includes an anodized aluminum body having a surface finish on the portion of the body adapted to support a substrate thereon of between about 200 to about 2000 micro-inches. In one embodiment, a substrate support assembly includes an electrically conductive body having a substrate support surface, a substrate support structure that is adapted to support the conductive body and the conductive body is covered by an electrically insulative coating.Type: GrantFiled: July 15, 2005Date of Patent: February 12, 2013Assignee: Applied Materials, Inc.Inventors: Soo Young Choi, Beom Soo Park, Quanyuan Shang, John M. White, Dong-Kil Yim, Chung-Hee Park
-
Patent number: 8361549Abstract: A method for preventing particle contamination within a processing chamber is disclosed. Preheating the substrate within the processing chamber may cause a thermophoresis effect so that particles within the chamber that are not adhered to a surface may not come to rest on the substrate. One method to increase the substrate temperature is to plasma load the substrate. Plasma loading comprises providing an inert gas plasma to the substrate to heat the substrate. Another method to increase the substrate temperature is high pressure loading the substrate. High pressure loading comprises heating the substrate while increasing the chamber pressure to between about 1 Torr and about 10 Torr. By rapidly increasing the substrate temperature within the processing chamber prior to substrate processing, particle contamination is less likely to occur.Type: GrantFiled: December 9, 2011Date of Patent: January 29, 2013Assignee: Applied Materials, Inc.Inventors: Dong-Kil Yim, John M. White, Soo Young Choi, Han Byoul Kim, Jin Man Ha, Beom Soo Park
-
Publication number: 20130017648Abstract: Embodiments of the disclosure provide methods of fabricating a thin film transistor device with good profile control of peripheral sidewall of an active layer formed in the thin film transistor devices. In one embodiment, a method for manufacturing a thin film transistor device includes providing a substrate having a source-drain metal electrode layer disposed on an active layer formed thereon, wherein the active layer is a metal oxide layer, performing a back-channel-etching process to form a channel in the source-drain metal electrode layer, and performing an active layer patterning process after the back-channel-etching process.Type: ApplicationFiled: June 30, 2012Publication date: January 17, 2013Applicant: Applied Materials, Inc.Inventor: Dong-Kil Yim
-
Publication number: 20130005081Abstract: The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source and drain electrodes are formed, but before the passivation layers or etch stop layers are deposited thereover, the active channel is exposed to an N2O or O2 plasma. The interface between the active channel and the passivation layers or etch stop layers are either altered or damaged during formation of the source and drain electrodes. The N2O or O2 plasma alters and repairs the interface between the active channel and the passivation or etch stop layers.Type: ApplicationFiled: June 7, 2012Publication date: January 3, 2013Applicant: Applied Materials, Inc.Inventors: JRJYAN JERRY CHEN, SOO YOUNG CHOI, DONG-KIL YIM, YAN YE
-
Patent number: 8173228Abstract: A method of reducing the amount of particulates generated from the surface of a processing component used during plasma enhanced chemical vapor deposition of thin films. The body of the processing component comprises an aluminum alloy, and an exterior surface of said processing component is texturized to increase the amount of surface area present on the exterior surface. The texturizing process includes at least one step in which the surface to be texturized is bead blasted or chemically grained, so that the surface roughness of the texturized surface ranges from about 50 ?-inch Ra to about 1,000 ?-inch Ra.Type: GrantFiled: August 2, 2006Date of Patent: May 8, 2012Assignee: Applied Materials, Inc.Inventors: Soo Young Choi, John M. White, Beom Soo Park, Dong Kil Yim
-
Publication number: 20120082802Abstract: A method for preventing particle contamination within a processing chamber is disclosed. Preheating the substrate within the processing chamber may cause a thermophoresis effect so that particles within the chamber that are not adhered to a surface may not come to rest on the substrate. One method to increase the substrate temperature is to plasma load the substrate. Plasma loading comprises providing an inert gas plasma to the substrate to heat the substrate. Another method to increase the substrate temperature is high pressure loading the substrate. High pressure loading comprises heating the substrate while increasing the chamber pressure to between about 1 Torr and about 10 Torr. By rapidly increasing the substrate temperature within the processing chamber prior to substrate processing, particle contamination is less likely to occur.Type: ApplicationFiled: December 9, 2011Publication date: April 5, 2012Inventors: Dong-Kil YIM, John M. WHITE, Soo Young CHOI, Beom Soo PArk, Han Byoul KIM, Jin Man HA
-
Publication number: 20120031335Abstract: The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple substrates are disposed on opposite sides of the processing source within the processing chamber, yet the processing environments are not isolated from each other. The processing source is a horizontally centered vertical plasma generator that permits multiple substrates to be processed simultaneously on either side of the plasma generator, yet independent of each other. The system is arranged as a twin system whereby two identical processing lines, each with their own processing chamber, are arranged adjacent to each other. Multiple robots are used to load and unload the substrates from the processing system. Each robot can access both processing lines within the system.Type: ApplicationFiled: April 29, 2011Publication date: February 9, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Shinichi Kurita, Jozef Kudela, Suhail Anwar, John M. White, Dong-Kil Yim, Hans Georg Wolf, Dennis Zvalo, Makoto Inagawa, Ikuo Mori
-
Publication number: 20120031333Abstract: The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple substrates are disposed on opposite sides of the processing source within the processing chamber, yet the processing environments are not isolated from each other. The processing source is a horizontally centered vertical plasma generator that permits multiple substrates to be processed simultaneously on either side of the plasma generator, yet independent of each other. The system is arranged as a twin system whereby two identical processing lines, each with their own processing chamber, are arranged adjacent to each other. Multiple robots are used to load and unload the substrates from the processing system. Each robot can access both processing lines within the system.Type: ApplicationFiled: April 29, 2011Publication date: February 9, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Shinichi Kurita, Jozef Kudela, Suhail Anwar, John M. White, Dong-Kil Yim, Hans Georg Wolf, Dennis Zvalo, Makoto Inagawa, Ikuo Mori
-
Patent number: 8076222Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.Type: GrantFiled: September 4, 2008Date of Patent: December 13, 2011Assignee: Applied Materials, Inc.Inventors: Tae Kyung Won, Soo Young Choi, Dong Kil Yim, Jriyan Jerry Chen, Beom Soo Park
-
Patent number: 8075952Abstract: A method for preventing particle contamination within a processing chamber is disclosed. Preheating the substrate within the processing chamber may cause a thermophoresis effect so that particles within the chamber that are not adhered to a surface may not come to rest on the substrate. One method to increase the substrate temperature is to plasma load the substrate. Plasma loading comprises providing an inert gas plasma to the substrate to heat the substrate. Another method to increase the substrate temperature is high pressure loading the substrate. High pressure loading comprises heating the substrate while increasing the chamber pressure to between about 1 Torr and about 10 Torr. By rapidly increasing the substrate temperature within the processing chamber prior to substrate processing, particle contamination is less likely to occur.Type: GrantFiled: June 29, 2006Date of Patent: December 13, 2011Assignee: Applied Materials, Inc.Inventors: Dong-Kil Yim, John M. White, Soo Young Choi, Han Byoul Kim, Jin Man Ha, Beom Soo Park
-
Patent number: 7955890Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.Type: GrantFiled: June 17, 2009Date of Patent: June 7, 2011Assignee: Applied Materials, Inc.Inventors: Soo Young Choi, Jriyan Jerry Chen, Tae Kyung Won, Dong-Kil Yim
-
Patent number: 7915114Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.Type: GrantFiled: November 27, 2007Date of Patent: March 29, 2011Assignee: Applied Materials, Inc.Inventors: Mark Hsiao, Dong-Kil Yim, Takako Takehara, Quanyuan Shang, William R. Harshbarger, Woong-Kwon Kim, Duk-Chul Yun, Youn-Gyung Chang
-
Patent number: 7833885Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.Type: GrantFiled: November 26, 2008Date of Patent: November 16, 2010Assignee: Applied Materials, Inc.Inventors: Tae Kyung Won, Soo Young Choi, Dong Kil Yim, Jriyan Jerry Chen, Beom Soo Park
-
Patent number: 7732010Abstract: A method for supporting a glass substrate comprising providing a substrate support having an aluminum body, a substrate contact area formed on the surface of the substrate support, wherein the process of forming the substrate contact area comprises forming an anodization layer on a surface region of the aluminum body, the coating having a thickness of between about 0.3 mils and about 2.16 mils, wherein the surface region substantially corresponds to the substrate contact area, and preparing the anodization layer disposed over the surface region to a surface roughness between about 88 micro-inches and about 230 micro-inches, followed by anodizing the substrate surface to said thickness, positioning the substrate support adjacent a substrate processing region in a substrate processing chamber, wherein the substrate contact area is adjacent the substrate processing region, positioning the glass substrate on the substrate contact area.Type: GrantFiled: April 18, 2006Date of Patent: June 8, 2010Assignee: Applied Materials, Inc.Inventors: Soo Young Choi, Beom Soo Park, Quanyuan Shang, Robert I. Greene, John M. White, Dong-Kil Yim, Chung-Hee Park, Kam Law
-
Publication number: 20100013626Abstract: Embodiments disclosed herein include a method and apparatus for supporting a substrate. When a substrate is inserted into a processing chamber by an end effector robot, the substrate is placed on one or more lift pins. The lift pins may include a sensing mechanism that can detect whether the substrate is cracked, the lift pin is broken, or the lift pin sticks to the bushing. By detecting the aforementioned conditions, uniform, repeatable deposition may be obtained for multiple substrates.Type: ApplicationFiled: July 13, 2009Publication date: January 21, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Chung-Hee Park, John M. White, Dong Kil Yim
-
Publication number: 20090315030Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.Type: ApplicationFiled: June 17, 2009Publication date: December 24, 2009Applicant: APPLIED MATERIALS, INC.Inventors: Soo Young Choi, Jriyan Jerry Chen, Tae Kyung Won, Dong-Kil Yim
-
Publication number: 20090200551Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.Type: ApplicationFiled: September 4, 2008Publication date: August 13, 2009Inventors: Tae Kyung Won, Soo Young Chol, Dong-Kil Yim, Jriyan Jerry Chen
-
Publication number: 20090200552Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.Type: ApplicationFiled: November 26, 2008Publication date: August 13, 2009Applicant: APPLIED MATERIALS, INC.Inventors: Tae Kyung Won, Soo Young Choi, Dong Kil Yim, Jriyan Jerry Chen, Beom Soo Park
-
Patent number: 7514936Abstract: Method and apparatus for detecting or suppressing electrical arcing or other abnormal change in the electrical impedance of a load connected to a power source. Preferably the load is a plasma chamber used for manufacturing electronic components such as semiconductors and flat panel displays. Arcing is detected by monitoring one or more sensors. Each sensor either responds to a characteristic of the electrical power being supplied by an electrical power source to the plasma or is coupled to the plasma chamber so as to respond to an electromagnetic condition within the chamber. Arcing is suppressed by reducing the power output for a brief period. Then the power source increases its power output, preferably to its original value. If the arcing resumes, the power source repeats the steps of reducing and then restoring the power output.Type: GrantFiled: October 27, 2007Date of Patent: April 7, 2009Assignee: Applied Materials, Inc.Inventors: Suhail Anwar, Remegio Manacio, Chung-Hee Park, Dong-Kil Yim, Soo Young Choi
-
Publication number: 20090064934Abstract: The present invention generally comprises a method and an apparatus for guiding the flow of processing gases away from chamber walls and slit valve opening. By controlling the flow path of the process gases within a processing chamber, undesirable deposition upon chamber walls and within slit valve openings may be reduced. By reducing deposition in slit valve openings, flaking may be reduced. By reducing deposition on chamber walls, the time between chamber cleaning may be increased. Thus, guiding the flow of processing gases within the processing chamber may increase substrate throughput.Type: ApplicationFiled: September 5, 2008Publication date: March 12, 2009Inventors: BEOM SOO PARK, Young Jin Choi, Robin L. Tiner, Sam H. Kim, Soo Young Choi, John M. White, Dong-Kil Yim