Patents by Inventor Dong-su Park
Dong-su Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970493Abstract: The present disclosure provides autotaxin (ATX) inhibitor compounds and compositions including said compounds. The present disclosure also provides methods of using said compounds and compositions for inhibiting ATX. Also provided are methods of preparing said compounds and compositions, and synthetic precursors of said compounds.Type: GrantFiled: October 4, 2021Date of Patent: April 30, 2024Assignee: ILDONG PHARMACEUTICAL CO., LTD.Inventors: Sung-Ku Choi, Yoon-Suk Lee, Sung-Wook Kwon, Kyung-Sun Kim, Jeong-Geun Kim, Jeong-Ah Kim, An-Na Moon, Sun-Young Park, Jun-Su Ban, Dong-Keun Song, Kyu-Sic Jang, Ju-Young Jung, Soo-Jin Lee
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Publication number: 20240128136Abstract: A wafer level package includes: a substrate; an element portion disposed on one surface of the substrate; a cap disposed on the substrate to cover the element portion; a connection portion electrically connected to the element portion; and a bonding portion disposed on an outer side of the connection portion, wherein the bonding portion is disposed on a first surface of one of the substrate and the cap, wherein one end portion of the connection portion is disposed on a second surface having a step difference from the first surface, and wherein the connection portion and the bonding portion are formed of a eutectic material.Type: ApplicationFiled: February 16, 2023Publication date: April 18, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook PARK, Seong Hun NA, Jae Hyun JUNG, Kwang Su KIM, Sung Jun LEE, Yong Suk KIM, Dong Hyun PARK
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Publication number: 20240113318Abstract: A polymer electrolyte membrane having improved chemical or mechanical durability is provided. The present disclosure relates to a polymer electrolyte membrane, and the polymer electrolyte membrane according to the present disclosure comprises a porous support and a composite layer containing a first ionomer filled in the porous support, wherein the polymer electrolyte membrane comprises a first segment having a first durability and a second segment having a second durability, and the first durability is higher than the second durability.Type: ApplicationFiled: September 17, 2021Publication date: April 4, 2024Inventors: Eun Su LEE, Dong Hoon LEE, Na Young KIM, Jung Hwa PARK, Hye Song LEE
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Patent number: 11944661Abstract: The present invention provides a pharmaceutical composition for prevention or treatment of a stress disease and depression, the pharmaceutical composition be safely useable without toxicity and side effects by using an extract of leaves of Vaccinium bracteatum Thunb., which is natural resource of Korea, so that the reduction of manufacturing and production costs and the import substitution and export effects can be expected through the replacement of a raw material for preparation with a plant inhabiting in nature.Type: GrantFiled: February 7, 2018Date of Patent: April 2, 2024Assignee: JEONNAM BIOINDUSTRY FOUNDATIONInventors: Chul Yung Choi, Dool Ri Oh, Yu Jin Kim, Eun Jin Choi, Hyun Mi Lee, Dong Hyuck Bae, Kyo Nyeo Oh, Myung-A Jung, Ji Ae Hong, Kwang Su Kim, Hu Won Kang, Jae Yong Kim, Sang O Pan, Sung Yoon Park, Rack Seon Seong
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Patent number: 11945864Abstract: A monoclonal antibody or an antigen-binding fragment thereof according to an embodiment of the present invention can bind to lymphocyte-activation gene 3 (LAG-3) including a heavy chain variable region and a light chain variable region and inhibit the activity thereof. Thus it is expected to be useful for the development of immunotherapeutic agents for various disorders that are associated with LAG-3.Type: GrantFiled: June 28, 2019Date of Patent: April 2, 2024Assignee: Y-BIOLOGICS INC.Inventors: Sang Pil Lee, Ji-Young Shin, Sunha Yoon, Yunseon Choi, Jae Eun Park, Ji Su Lee, Youngja Song, Gisun Baek, Seok Ho Yoo, Yeung-chul Kim, Dong Jung Lee, Bum-Chan Park, Young Woo Park
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Publication number: 20240107032Abstract: The present invention relates to an image encoding and decoding technique, and more particularly, to an image encoder and decoder using unidirectional prediction. The image encoder includes a dividing unit to divide a macro block into a plurality of sub-blocks, a unidirectional application determining unit to determine whether an identical prediction mode is applied to each of the plurality of sub-blocks, and a prediction mode determining unit to determine a prediction mode with respect to each of the plurality of sub-blocks based on a determined result of the unidirectional application determining unit.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, University-Industry Cooperation Group of Kyung Hee UniversityInventors: Hae Chul CHOI, Se Yoon JEONG, Sung-Chang LIM, Jin Soo CHOI, Jin Woo HONG, Dong Gyu SIM, Seoung-Jun OH, Chang-Beom AHN, Gwang Hoon PARK, Seung Ryong KOOK, Sea-Nae PARK, Kwang-Su JEONG
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Publication number: 20240094364Abstract: Disclosed herein is an image sensing apparatus including a driver disposed on a substrate and configured to drive a light emitter and a light receiver to emit a first optical signal toward an object and receive a second optical signal reflected from the object, a housing coupled to the substrate and surrounding the light emitter, the light receiver, and the driver, a diffuser disposed on the housing, and a transparent electrode disposed on the diffuser, wherein the driver includes a transparent electrode driver configured to detect whether the diffuser is damaged in a first mode and shields electromagnetic interference noise in a second mode by using the transparent electrode.Type: ApplicationFiled: September 20, 2023Publication date: March 21, 2024Applicant: LX SEMICON CO., LTD.Inventors: Dong Su HAN, Jung Whan KIM, Seong Hong PARK
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Publication number: 20240097218Abstract: Methods and systems for executing tracking and monitoring manufacturing data of a battery are disclosed. One method includes: receiving, by a server system, sensing data of the battery from a sensing system; generating, by the server system, mapping data based on the sensing data; generating, by the server system, identification data of the battery based on the sensing data; generating, by the server system, monitoring data of the battery based on the sensing data, the identification data, and the mapping data; and generating, by the server system, display data for displaying a simulated electrode of the battery on a graphical user interface based on the monitoring data of the battery.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Inventors: Min Kyu Sim, Jong Seok Park, Min Su Kim, Jae Hwan Lee, Ki Deok Han, Eun Ji Jo, Su Wan Park, Gi Yeong Jeon, June Hee Kim, Wi Dae Park, Dong Min Seo, Seol Hee Kim, Dong Yeop Lee, Jun Hyo Su, Byoung Eun Han, Seung Huh
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Publication number: 20240085668Abstract: An optical imaging system includes a first lens having positive refractive power, a second lens having negative refractive power, a third lens, a fourth lens, a fifth lens, a sixth lens, a seventh lens, and an eighth lens disposed in order from an object side. A refractive index of the second lens is greater than a refractive index of each of the first lens and the third lens. The optical imaging system satisfies TTL/(2×IMG HT)<0.6 and 0<f1/f<1.4, where TTL is a distance on an optical axis from an object-side surface of the first lens to an imaging plane, IMG HT is half a diagonal length of the imaging plane, f is a total focal length of the optical imaging system, and f1 is a focal length of the first lens.Type: ApplicationFiled: May 18, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dong Hyuk JANG, Ji Su LEE, Il Yong PARK
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Publication number: 20240080011Abstract: A bulk-acoustic wave (BAW) resonator includes a central portion in which a first electrode, a piezoelectric layer, and a second electrode are sequentially stacked on a substrate, and an extension portion extending externally from the central portion, and an insertion layer and a loss prevention film are disposed in the extension portion between the substrate and the second electrode. The loss prevention film is formed to have a thickness of 50 ? to 500 ?. The insertion layer is stacked on the loss prevention film, and has a side surface opposing the central portion, the side surface is formed as a first inclined surface having a first inclination angle. The loss prevention film has a side surface opposing the central portion, the side surface is formed as a second inclined surface having a second inclination angle. The second inclination angle is formed to be greater than the first inclination angle.Type: ApplicationFiled: February 22, 2023Publication date: March 7, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Moon Chul LEE, Jae Hyoung GIL, Kwang Su KIM, Sung Jun LEE, Yong Suk KIM, Dong Hyun PARK, Tae Kyung LEE
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Patent number: 11826777Abstract: A method of modifying the surface of a coating layer applied to a substrate includes a step (s1) of preparing a substrate by performing pretreatment, a step (s2) of coating the substrate with a coating layer, and a step (s3) of modifying the surface of the coating layer by vibrating the substrate in the vertical direction. The surface modification method does not include a separate chemical process.Type: GrantFiled: January 12, 2022Date of Patent: November 28, 2023Assignee: GACHON UNIVERSITY OF INDUSTRY—ACADEMIC COOPERATION FOUNDATIONInventors: Kyoung Su Park, Dong Su Park
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Publication number: 20220219196Abstract: A method of modifying the surface of a coating layer applied to a substrate is disclosed. The surface modification method includes a step (s1) of preparing a substrate by performing pretreatment, a step (s2) of coating the substrate with a coating layer, and a step (s3) of modifying the surface of the coating layer by vibrating the substrate in the vertical direction. The surface modification method does not include a separate chemical process and is thus environmentally friendly and economically advantageous.Type: ApplicationFiled: January 12, 2022Publication date: July 14, 2022Applicant: GACHON UNIVERSITY OF INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Kyoung Su PARK, Dong Su PARK
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Patent number: 11322501Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: GrantFiled: July 1, 2020Date of Patent: May 3, 2022Assignee: SK hynix Inc.Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
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Patent number: 11217592Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: GrantFiled: January 16, 2020Date of Patent: January 4, 2022Assignee: SK hynix Inc.Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
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Publication number: 20200335505Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
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Patent number: 10734389Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: GrantFiled: October 8, 2019Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
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Publication number: 20200152637Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
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Patent number: 10580777Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: GrantFiled: January 9, 2018Date of Patent: March 3, 2020Assignee: SK hynix Inc.Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
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Publication number: 20200043933Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: ApplicationFiled: October 8, 2019Publication date: February 6, 2020Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
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Patent number: 10483265Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.Type: GrantFiled: December 27, 2018Date of Patent: November 19, 2019Assignee: SK hynix Inc.Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang