Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: A Micro-Secure Digital (“SD”) device loaded with a smart card that can be issued in bulk and in card form is provided. The device includes: a SD interface electrically connected to a host terminal; at least one memory module; a SD controller connected to the SD interface to provide communication between a host terminal and the memory module; at least one smart card IC for data communication with the SD controller; and a smart card interface for issuing smart cards. Since the Micro-SD device is provided with a smart card function and a card form satisfying the ISO 7810 standard, it may be issued in bulk through automation using a conventional automatic card-issuing device that automatically issues a credit card or a USIM card.

Abstract: A creep tester for a precise and accurate creep test includes a movable actuator capable of loading corresponding to change in length of a specimen, a cam actuator operated in association with the movable actuator, and a self weight actuator. The movable actuator includes upper and lower spherical adjusting seats to hold upper and lower portions of the specimen, a spring disposed on the upper spherical adjusting seat to correspond to a minute deformation of the specimen, upper and lower movable tables respectively contacting the spring and the lower spherical adjusting seat, a load cell and a stationary table disposed on the upper movable table, and a movable loading table disposed below the lower movable table to apply a predetermined load to the specimen. The creep tester can perform a precise creep test by continuously applying a constant load without supplementation of hydraulic pressure.

Abstract: Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and an upper metal interconnection layer disposed on the intermetallic dielectric layer and electrically connected through the intermetallic dielectric layer and buffer layer to the lower metal interconnection layers.

Abstract: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.

Abstract: Disclosed is a method and apparatus for rotating a heavy weight object by coincidence of centers of gravity. The apparatus includes a fixing frame unit to fix the weight object; a weight object rotating unit accommodating the weight object, including a rotatable semicircular frame, and connected to the fixing frame unit; a weight object/frame support unit formed under the semicircular frame to support the semicircular frame; and a motor/gear unit formed between the weight object rotating unit and the weight object/frame support unit to rotate the weight object rotating unit using bearings. The apparatus rotates the weight object even when the minimum force is applied to the weight object through the weight object rotating unit, has a minimized radius of rotation, and secures the safety, thus being applied to a production and assembly line in a narrow space to produce weight objects or a structural test building.

Abstract: A creep tester for a precise and accurate creep test includes a movable actuator capable of loading corresponding to change in length of a specimen, a cam actuator operated in association with the movable actuator, and a self weight actuator. The movable actuator includes upper and lower spherical adjusting seats to hold upper and lower portions of the specimen, a spring disposed on the upper spherical adjusting seat to correspond to a minute deformation of the specimen, upper and lower movable tables respectively contacting the spring and the lower spherical adjusting seat, a load cell and a stationary table disposed on the upper movable table, and a movable loading table disposed below the lower movable table to apply a predetermined load to the specimen. The creep tester can perform a precise creep test by continuously applying a constant load without supplementation of hydraulic pressure.

Abstract: A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers.

Abstract: A method for fabricating a semiconductor device having a bulb-type recessed channel including forming a mask layer on the semiconductor substrate to expose a region where a trench for a bulb-type recessed channel can be formed, forming the trench in the semiconductor substrate, implanting dopant ions in three-dimensional radial directions with a predetermined tilt angle in the exposed region of the semiconductor substrate, removing the mask layer, forming a gate stack in the region including the trench, and forming a source/drain in the semiconductor substrate.

Abstract: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.

Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection.

Abstract: A method for forming a dual poly gate of a semiconductor device includes forming a gate insulating layer on a semiconductor substrate having a first region and a second region; forming an amorphous silicon layer, in which a portion defined by the first region is implanted with impurity ions of a first conductivity type and a portion defined by the second region is implanted with impurity ions of a second conductivity type, on the gate insulating layer; forming silicon seeds on the amorphous silicon layer; forming hemispherical grains on the surface of the amorphous silicon layer using the silicon seeds; and activating the implanted impurity ions and crystallizing the amorphous silicon layer having the hemispherical grains formed thereon by annealing to form a polysilicon layer of a first conductivity type and a polysilicon layer of a second conductivity type in the portions of the amorphous silicon layer defined by the first and second regions, respectively.

Abstract: A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.

Abstract: Disclosed herein is a metal interconnection structure of a semiconductor device, comprising lower metal interconnection layers disposed on a semiconductor substrate, a buffer layer made of a metal oxide disposed thereon, an intermetallic dielectric layer made of a low-k material disposed on the buffer layer of the metal oxide, and an upper metal interconnection layer disposed on the intermetallic dielectric layer and electrically connected through the intermetallic dielectric layer and buffer layer to the lower metal interconnection layers.

Abstract: The present invention discloses methods for manufacturing a capacitor of a semiconductor device employing doped silicon film as an electrode and an oxide film-nitride film-oxide film as a dielectric film. An interlayer insulating film is formed on a semiconductor substrate. A storage electrode is formed consisting of a doped polysilicon on the interlayer insulating film. A first oxide film is formed on the storage electrode that is subjected to a thermal treatment in an atmosphere containing an n-type impurity to implant the impurity into the first oxide film. A nitride film is formed on the first oxide film, whereby the impurity in the first oxide film is diffused into the nitride film. A second oxide film is formed on the nitride film. A plate electrode is then formed on the second oxide film.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming a gate in a cell region and a peripheral region of a substrate, depositing a buffer oxide layer on the gate and the substrate, annealing a resultant structure of the substrate, depositing a nitride spacer layer on the buffer oxide layer, depositing an oxide spacer layer on the nitride spacer layer, forming an oxide spacer at the peripheral region of the substrate, and removing the oxide spacer layer remaining in the cell region. The annealing step is additionally carried out after depositing the buffer oxide layer so as to improve the interfacial surface characteristic and film quality, so that oxide etchant is prevented from penetrating into the silicon substrate during the wet dip process. Unnecessary voids are prevented from being created in the silicon substrate.

Abstract: The present invention discloses a method for manufacturing semiconductor device wherein a cleaning process of a buffer layer is performed prior to a formation of a nitride film. The cleaning process allows to maintain the deposition thickness of the nitride film even when the time between the formation of the buffer layer and the formation of the nitride film is long.