Patents by Inventor Douglas D. Coolbaugh
Douglas D. Coolbaugh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9171778Abstract: A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.Type: GrantFiled: January 28, 2014Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8881379Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.Type: GrantFiled: May 1, 2012Date of Patent: November 11, 2014Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Terence B. Hook, Robert M. Rassel, Edmund J. Sprogis, Anthony K. Stamper, William J. Murphy
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Patent number: 8872281Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.Type: GrantFiled: August 9, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Lie, James S. Nakos, Bradley A. Omer, Robert M. Rassel, David C. Sheridan
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Publication number: 20140239498Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.Type: ApplicationFiled: August 9, 2012Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Liu, James S. Nakos, Bradley A. Orner, Robert M. Rassel, David C. Sheridan
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Patent number: 8753950Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: March 28, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8749293Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.Type: GrantFiled: June 21, 2012Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Fen Chen, Douglas D. Coolbaugh, Baozhen Li
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Publication number: 20140151899Abstract: A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.Type: ApplicationFiled: January 28, 2014Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. COOLBAUGH, Keith E. DOWNES, Peter J. LINDGREN, Anthony K. STAMPER
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Patent number: 8609505Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.Type: GrantFiled: January 26, 2012Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Robert M. Rassel, Anthony K. Stamper
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Patent number: 8435864Abstract: A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: GrantFiled: March 28, 2012Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Patent number: 8378450Abstract: An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.Type: GrantFiled: August 27, 2009Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He
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Patent number: 8338265Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.Type: GrantFiled: November 12, 2008Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Liu, James S. Nakos, Bradley A. Orner, Robert M. Rassel, David C. Sheridan
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Patent number: 8294505Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.Type: GrantFiled: August 23, 2005Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Fen Chen, Douglas D. Coolbaugh, Baozhen Li
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Publication number: 20120261724Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.Type: ApplicationFiled: June 21, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen Chen, Douglas D. Coolbaugh, Baozhen Li
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Publication number: 20120214280Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.Type: ApplicationFiled: May 1, 2012Publication date: August 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. COOLBAUGH, Ebenezer E. ESHUN, Terence B. HOOK, Robert M. RASSEL, Edmund J. SPROGIS, Anthony K. STAMPER, William J. MURPHY
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Patent number: 8236663Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: September 22, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J Lindgren, Anthony K. Stamper
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Patent number: 8230586Abstract: A method of cooling a resistor is provided. The method includes forming a first electrical insulator having a high thermal conductivity in thermal contact with an electrically resistive pathway and forming a substrate adjacent the electrical insulator. The method further includes forming a first electrical conductor having a high thermal conductivity within the second substrate and in thermal contact with the electrical insulator.Type: GrantFiled: August 31, 2007Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Douglas D Coolbaugh, Ebenezer E Eshun, Terence B Hook, Robert M Rassel, Edmund J Sprogis, Anthony K Stamper, William J Murphy
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Publication number: 20120190164Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: ApplicationFiled: March 28, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. COOLBAUGH, Keith E. DOWNES, Peter J. LINDGREN, Anthony K. STAMPER
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Patent number: 8227849Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.Type: GrantFiled: February 17, 2010Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Ebenezer E Eshun, Ronald J Bolam, Douglas D Coolbaugh, Keith E Downes, Natalie B Feilchenfeld, Zhong-Xiang He
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Publication number: 20120184081Abstract: A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: ApplicationFiled: March 28, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil K. CHINTHAKINDI, Douglas D. COOLBAUGH, Keith E. DOWNES, Ebenezer E. ESHUN, Zhong-Xiang HE, Robert M. RASSEL, Anthony K. STAMPER
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Patent number: 8207568Abstract: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: GrantFiled: September 19, 2005Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper