Abstract: In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Abstract: A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.

Abstract: A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.

Abstract: A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.

Abstract: An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used to determine which of two possible modes of operation, a referenceless or reference clock mode of operation, is used based on a detected frequency of an externally-provided frequency reference signal. The frequency is detected without any additional externally provided signal to indicate the mode of operation or the frequency of the reference clock. If the frequency detection circuit detects a frequency below a predetermined threshold, referenceless mode of operation is indicated. Otherwise, reference clock mode of operation is indicated. In referenceless mode of operation such operations as frequency acquisition and lock detect are performed without the use of a reference clock. In reference clock mode the reference clock is used for such operations as frequency acquisition and lock detect.

Abstract: Byte synchronization between a bus master and a serial interface or other bus slave is maintained and promptly corrected by using a unique signal, issued by the serial interface, to promptly and unambiguously notify the bus master of a loss of synchronization, followed by prompt resynchronization by the bus master. The serial interface sets a selected indicium in a status register equal to a selected value, when an invalid command is sensed at the interface. The bus master reads the status register and, when the selected indicium has the selected value, promptly resynchronizes the serial interface without further delay.

Abstract: A slice and offset circuit is provided that uses a digital integrator in the feedback loop of the offset cancellation circuitry. A slice circuit receives an indication of a desired slice voltage and supplies a signal to specify the slice level, which is combined with a sensed offset level of the amplifier. The feedback loop includes a low pass filter that receives the combined signal indicative of the offset and the slice level. The low pass filter includes the digital integrator circuit that includes an up/down counter that counts in a direction determined according to a digital signal having a ones-density indicative of a value of the combined signal with respect to a reference signal, thereby generating a feedback signal that cancels offset and adjusts for slice.

Abstract: Byte synchronization between a bus master and a serial interface or other bus slave is maintained and promptly corrected by using a unique signal, issued by the serial interface, to promptly and unambiguously notify the bus master of a loss of synchronization, followed by prompt resynchronization by the bus master. The serial interface sets a selected indicium in a status register equal to a selected value, when an invalid command is sensed at the interface. The bus master reads the status register and, when the selected indicium has the selected value, promptly resynchronizes the serial interface without further delay.

Abstract: A serial interface or port is configured so that: a Read command and a Write command can be performed substantially simultaneously; a shortened Read command, followed by another Read command, can be performed in reduced time, due to the shortening of the first Read command; and a continuous stream of Read commands can be performed consecutively with no time delay By performing Read and Write commands simultaneously on associated channels at a serial interface, the time required for such performance is reduced by as much as 50 percent.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: An energy-to-pulse (E2P) converter for converting analog voltage and current measurements into digital power consumption readout that has an improved output frequency range and can eliminate the potential information loss in a multiple-wires and multiple-phases power distribution system without added complex hardware. The E2P uses a threshold value T in determining the output pulse count which represents the energy/power consumption. The energy consumption E is updated every cycle of a first clock rate F1 during which a power P calculation is performed following a voltage V and a current I analog-to digital conversion. The updated energy consumption E is then divided by the threshold value T to determine the number of pulses that correspond to the power consumption. The number of pulses are output at a second clock rate F2. In so doing, more than one pulse can be generated for each P calculation thereby improving the output frequency range.

Abstract: A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is held high for a predetermined period of time, the one-shot is triggered and a SLEEP signal is generated. The device reacts to this SLEEP signal by entering a sleep mode. Similarly, if the SCLK signal is held low for a predetermined period of time, the one-shot may output a low level RESET signal. This RESET signal resets the device into an initial condition state. Other modes of operation, such as test modes and the like may be entered into by holding the SCLK signal high or low in conjunction with a predetermined logic level on another pin (e.g., VREF).

Abstract: An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase 2 or 3 wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

Abstract: The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V+supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals INH and INL may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V+ and V−.

Abstract: Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to &Dgr;I-&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to &Dgr;I−&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value.

Abstract: A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.