Abstract: A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.