Abstract: A method is provided for forming a reflective plasmonic display. The method provides a substrate and deposits a bottom dielectric layer. A conductive film is deposited overlying the bottom dielectric layer. A hard mask is formed with nano-size openings overlying the conductive film. The conductive film is plasma etched via nano-size openings in the hard mask, stopping at the dielectric layer. After removing the hard mask, a conductive film is left with nano-size openings to the dielectric layer. Metal is deposited in the nano-size openings, creating a pattern of metallic nanoparticles overlying the dielectric layer. Then, the conductive film is removed. The hard mask may be formed by conformally depositing an Al film overlying the conductive film and anodizing the Al film, creating a hard mask of porous anodized Al oxide (AAO) film. The porous AAO film may form a short-range hexagonal, and long-range random order hole patterns.

Abstract: A plasmonic polarizer and a method for fabricating the plasmonic polarizer are provided. The method deposits alternating layers of non-metallic film and metal, forming a stack. A hard mask is formed overlying the stack. The hard mask comprises structures having dimensions and periods between adjacent structures less than a first length, where the first length is equal to (a first wavelength of light/2). The stack is etched through openings in the hard mask to form pillar stacks of alternating non-metallic and metal layers having the dimensions of the hard mask structures. Then, the hard mask structures are removed. In one aspect, subsequent to removing the hard mask structures, the spaces between the pillar stacks are filled with a dielectric material.

Abstract: A plasmonic optical device is provided operating in near ultra violet (UV) and visible wavelengths of light. The optical device is made from a substrate and nanoparticles. The nanoparticles have a core with a negative real value relative permittivity of absolute value greater than 10 in a first range of wavelengths including near UV and visible wavelengths of light, and a shell with an imaginary relative permittivity of less than 5 in the first range of wavelengths. A dielectric overlies the substrate, and is embedded with the nanoparticles. If the substrate is reflective, a reflective optical filter is formed. If the substrate is transparent, the filter is transmissive. In one aspect, the dielectric is a tunable medium (e.g., liquid crystal) having an index of refraction responsive to an electric field. The tunable medium is interposed between a first electrode and a second electrode.

Abstract: Methods are provided for fabricating a multi-structure pore membrane. In one method, an anodized aluminum oxide (AAO) template is formed with an array of pores exposing underlying regions of a conductive layer top surface. A plurality of photoresist layers is patterned to sequentially expose a plurality of AAO template sections. Each exposed AAO template section is sequentially etched to widen pore diameters, so that each AAO template section may be associated with a corresponding unique pore diameter. A target material is deposited in the pores of the AAO template and, as a result, an array of target material structures is formed on the top surface, where the target material structures associated with each AAO template section have a corresponding diameter. Also provided is a multi-structure pixel device formed with subpixels having different structure dimensions.

Abstract: A plasmonic polarizer and a method for fabricating the plasmonic polarizer are provided. The method deposits alternating layers of non-metallic film and metal, forming a stack. A hard mask is formed overlying the stack. The hard mask comprises structures having dimensions and periods between adjacent structures less than a first length, where the first length is equal to (a first wavelength of light/2). The stack is etched through openings in the hard mask to form pillar stacks of alternating non-metallic and metal layers having the dimensions of the hard mask structures. Then, the hard mask structures are removed. In one aspect, subsequent to removing the hard mask structures, the spaces between the pillar stacks are filled with a dielectric material.

Abstract: A method is provided for forming a reflective plasmonic display. The method provides a substrate and deposits a bottom dielectric layer. A conductive film is deposited overlying the bottom dielectric layer. A hard mask is formed with nano-size openings overlying the conductive film. The conductive film is plasma etched via nano-size openings in the hard mask, stopping at the dielectric layer. After removing the hard mask, a conductive film is left with nano-size openings to the dielectric layer. Metal is deposited in the nano-size openings, creating a pattern of metallic nanoparticles overlying the dielectric layer. Then, the conductive film is removed. The hard mask may be formed by conformally depositing an Al film overlying the conductive film and anodizing the Al film, creating a hard mask of porous anodized Al oxide (AAO) film. The porous AAO film may form a short-range hexagonal, and long-range random order hole patterns.

Abstract: A full color complementary metal oxide semiconductor (CMOS) imaging circuit is provided. The imaging circuit is made up of an array of photodiodes including a plurality of pixel groups. Each pixel group supplies 3 electrical color signals, corresponding to 3 detectable colors. A color filter array overlies the photodiode array employing less than 3 separate filter colors. Each pixel group may be enabled as a dual-pixel including a single photodiode (PD) to supply a first color signal and stacked PDs to supply a second and third color signal. In one aspect, the color filter array employs 1 filter color per pixel group. In another aspect, the color filter array employees 2 filter colors per pixel group. In either aspect, the color filter array forms a checkerboard pattern of color filter pixels. For example, a magenta color filter may overlie the stacked PDs of each dual-pixel, to name one variation.

Abstract: A full color range analog controlled interferometric modulation device is provided. The device includes a transparent substrate, and a transparent fixed-position electrically conductive electrode with a bottom surface overlying the substrate. A transparent spacer overlies the fixed-position electrode, and an induced absorber overlies the spacer. An optically reflective electrically conductive moveable membrane overlies the induced absorber. A cavity is formed between the induced absorber and the moveable membrane having a maximum air gap dimension less than the spacer thickness. In one aspect, the distance from the top surface of the fixed-position electrode to a cavity lower surface is at least twice as great as the cavity maximum air gap dimension. In another aspect, at least one anti-reflective coating (ARC) layer is interposed between the substrate and the fixed-position electrode, and at least one ARC layer is interposed between the fixed-position electrode and the spacer.

Abstract: A method of providing a layer in a semiconductor device, wherein the layer includes Si1-x-yGexCy, and wherein the carbon in the layer is in a stable condition, includes preparing a silicon substrate; preparing a SiGeC precursor; forming a Si1-x-yGexCy layer on the silicon substrate from the precursor; forming a top silicon layer on the Si1-x-yGexCy layer; and completing the semiconductor device.

Abstract: A full color range analog controlled interferometric modulation device is provided. The device includes a transparent substrate, and a transparent fixed-position electrically conductive electrode with a bottom surface overlying the substrate. A transparent spacer overlies the fixed-position electrode, and an induced absorber overlies the spacer. An optically reflective electrically conductive moveable membrane overlies the induced absorber. A cavity is formed between the induced absorber and the moveable membrane having a maximum air gap dimension less than the spacer thickness. In one aspect, the distance from the top surface of the fixed-position electrode to a cavity lower surface is at least twice as great as the cavity maximum air gap dimension. In another aspect, at least one anti-reflective coating (ARC) layer is interposed between the substrate and the fixed-position electrode, and at least one ARC layer is interposed between the fixed-position electrode and the spacer.

Abstract: An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array is provided. The array is built upon a lightly doped p doped silicon (Si) substrate. Each pixel cell includes at least one visible light detection pixel and an IR pixel. Each visible light pixel includes a moderately p doped bowl with a bottom p doped layer and p doped sidewalls. An n doped layer is enclosed by the p doped bowl, and a moderately p doped surface region overlies the n doped layer. A transfer transistor has a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region. The IR pixel is the same, except that there is no bottom p doped layer. An optical wavelength filter overlies the visible light and IR pixels.

Abstract: A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

Abstract: A dual-pixel full color CMOS imager comprises a two-photodiode stack including an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer at a first depth overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. A single photodiode including a bottom p doped layer overlies the substrate at a third depth. The third depth is less than, or equal to the first depth. A bottom n doped layer overlies the bottom p doped layer, a top p doped layer directly overlies the bottom n doped layer without an intervening layer, and a top n doped layer overlies the top p doped layer.

Abstract: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

Abstract: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

Abstract: Aspects of the present invention are related to systems and methods for image demosaicing.

Abstract: An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array is provided. The array is built upon a lightly doped p doped silicon (Si) substrate. Each pixel cell includes at least one visible light detection pixel and an IR pixel. Each visible light pixel includes a moderately p doped bowl with a bottom p doped layer and p doped sidewalls. An n doped layer is enclosed by the p doped bowl, and a moderately p doped surface region overlies the n doped layer. A transfer transistor has a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region. The IR pixel is the same, except that there is no bottom p doped layer. An optical wavelength filter overlies the visible light and IR pixels.

Abstract: A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.