Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

Abstract: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxia

Abstract: A SiGe surface-normal optical path photodetector structure and a method for forming the SiGe optical path normal structure are provided. The method comprises: forming a Si substrate with a surface; forming a Si feature, normal with respect to the Si substrate surface, such as a via, trench, or pillar; depositing SiGe overlying the Si normal feature to a thickness in the range of 5 to 1000 nanometers (nm); and, forming a SiGe optical path normal structure having an optical path length in the range of 0.1 to 10 microns. Typically, the SiGe has a Ge concentration in the range from 5 to 100%. The Ge concentration may be graded to increase with respect to the deposition thickness. For example, the SiGe may have a 20% concentration of Ge at the Si substrate interface, a 30% concentration of Ge at a SiGe film top surface, and a thickness of 400 nm.

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Abstract: A method of fabricating a silicon integrated circuit on a glass substrate includes preparing a glass substrate; fabricating a silicon layer on the glass substrate; implanting ions into the active areas of the silicon layer; covering the silicon layer with a heat pad material; activating the ions in the silicon layer by annealing while maintaining the glass substrate at a temperature below that of the thermal stability of the glass substrate; removing the heat pad material; and completing the silicon integrated circuit.

Abstract: A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 ? to 1 ?m below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Abstract: Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.

Abstract: A method of fabricating a germanium film on a silicon substrate includes preparing a silicon substrate; depositing a first germanium film to form a continuous germanium film on the silicon substrate; annealing the silicon substrate and the germanium film thereon in a first annealing process to relax the germanium film; depositing a second germanium film on the first germanium film to form a germanium layer; patterning and etching the germanium layer; depositing a layer of dielectric material on the germanium layer; cyclic annealing the silicon substrate having the germanium layer and dielectric material thereon; and completing a device containing the silicon substrate and germanium layer.

Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 10%, implanting H2+ ions through the SiGe layer into the substrate at a dose of between about 2×1014 cm?2 to 2×1016 cm?2, at an energy of between about 20 keV to 100+ keV; low temperature thermal annealing at a temperature of between about 200° C. to 400° C. for between about ten minutes and ten hours; high temperature thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 1000° C. for between about 30 seconds and 30 minutes; and depositing a layer of silicon-based material on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

Abstract: A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates; forming a first relaxed SiGe layer on the silicon substrate; forming a first tensile-strained silicon cap on the first relaxed SiGe layer; forming a second relaxed SiGe layer on the first tensile-strained silicon cap; forming a second tensile-strained silicon cap on the second relaxed SiGe layer; and completing an IC device.

Abstract: A method of fabricating a germanium photodetector includes preparing a silicon wafer as a silicon substrate; depositing a layer of silicon nitride on the silicon substrate; patterning and etching the silicon nitride layer; depositing a first germanium layer on the silicon nitride layer; patterning and etching the germanium layer wherein a portion of the germanium layer is in direct physical contact with the silicon substrate; depositing a layer of silicon oxide on the germanium layer wherein the germanium layer is encapsulated by the silicon oxide layer; annealing the structure at a temperature wherein the germanium melts and the other layers remain solid; growing a second, single-crystal layer of germanium on the structure by liquid phase epitaxy; selectively removing the silicon oxide layer; and completing the germanium photodetector.

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

Abstract: A 3D quantum dot optical path structure is provided, along with a method for selectively forming a 3D quantum dot optical path. The method comprises: forming a single crystal Si substrate with a surface; forming a Si feature in the substrate, such as a via, trench, or pillar; forming dots from a Ge or SiGe material overlying the Si feature; and, forming an optical path that includes the dots. In some aspects of the method, the Si feature has defect sites. For example, the Si feature may be formed with a miscut angle. As a result of the miscut angle, steps are formed in the Si feature plane. Then, the dots are formed in the Si feature steps. The miscut angle is in the range between 0.1 and 5 degrees, and the spacing between steps is in the range between 1 and 250 nanometers (nm).

Abstract: A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 ?; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 ?; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.

Abstract: A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium layer; preparing an insulator substrate; bonding the silicon/silicon-germanium portion to the insulator substrate with the silicon-germanium layer in contact with the insulator substrate to form a bonded entity; curing the bonded entity; and thermally annealing the bonded entity to split the bonded entity into a silicon/silicon germanium portion and a silicon-germanium-on-insulator portion and to relax the silicon germanium layers.

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Abstract: A method is provided for forming a relaxed single-crystal silicon germanium film on a silicon substrate. Also provided is a film structure with a relaxed layer of graded silicon germanium on a silicon substrate. The method comprises: providing a silicon (Si) substrate with a top surface; growing a graded layer of strained single-crystal Si1−xGex having a bottom surface overlying the Si substrate top surface and a top surface, where x increases with the Si1−xGex layer thickness in the range between 0.03 and 0.

Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of strained SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 20%, by molecular weight; implanting H2+ ions into the SiGe layer; irradiating the substrate and SiGe layer, to relax the SiGe layer; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

Abstract: Methods of forming a SiGe layer overlying an insulator are provided. A layer of SiGe is deposited on a substrate and implanted with ion to form a defect region within the SiGe material below its surface. The SiGe layer is then patterned and transferred by contact bonding to an insulator on a second substrate. After contact bonding the structure is annealed to split the SiGe layer along the defect region. The splitting anneal will relax the SiGe layer. Additional annealing at higher temperatures may be used to further relax the SiGe layer. A layer of strained silicon may then be epitaxial deposited on the resulting structure of relaxed SiGe on insulator. Another method provides for epitaxially depositing a layer of silicon over the SiGe layer prior to patterning. The silicon layer would then be bonded to the insulator on the second substrate. The splitting anneal and additional anneals, if any, should then induce strain into the silicon layer.