Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

Abstract: A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 ?; forms a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 ?; forms a layer of strained-Si overlying the first and second SiGe layers; forms a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forms an p-well in the substrate and the overlying first layer of SiGe; forming forms a p-well in the substrate and the overlying second layer of SiGe; forms channel regions, in the strained-Si, and forms PMOS and NMOS transistor source and drain regions.

Abstract: A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

Abstract: A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

Abstract: A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the contact holes. An N+ germanium layer is formed by ELO. The structure is smoothed and thinned. An intrinsic germanium layer is grown on the N+ epitaxial germanium layer. A P+ germanium layer is formed on the intrinsic germanium layer and a silicon oxide overcoat is deposited. A window is opened through the silicon oxide overcoat to the P+ germanium layer. A layer of conductive material is deposited on the silicon oxide overcoat and in the windows therein. The conductive material is etched to form individual sensing elements.

Abstract: A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the sacrificial Ge-containing film. The Si film surface is bonded to a transparent substrate, forming a bonded substrate. The bonded substrate is immersed in a Ge etching solution to remove the sacrificial Ge-containing film, which separates the transparent substrate from the Si wafer. The result is a transparent substrate with an overlying single crystal Si film. Optionally, channels can be formed to distribute the Ge etching solution, and promote the removal of the Ge-containing film.

Abstract: A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.

Abstract: A method of fabricating a germanium photo detector includes preparing a silicon substrate; depositing and planarizing a silicon oxide layer; forming contact holes in the silicon oxide layer which communicate with the underlying silicon substrate; growing an epitaxial germanium layer of a first type on the silicon oxide layer and in the contact holes; growing an intrinsic germanium layer on the epitaxial germanium layer and any exposed silicon oxide layer; growing a germanium layer of a second type on the intrinsic germanium layer and any exposed silicon oxide layer; depositing a layer of covering material take from the group of materials consisting of polysilicon, polysilicon-germanium and In2O3—SnO2; and etching the covering material to form individual sensing elements.

Abstract: A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

Abstract: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

Abstract: A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

Abstract: A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface. Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer having vertical silicon (111) sidewalls. Removing the mask; growing SiGe-containing layers on the patterned silicon (110) layer; and fabricating a photodetector.

Abstract: A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

Abstract: A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

Abstract: An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p?/p/p?/p layered structure.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: A method of fabricating a silicon-on-glass layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; relaxing the SiGe layer; depositing a layer of silicon on the relaxed SiGe layer; implanting hydrogen ions in a second hydrogen implantation step to facilitate splitting of the wafer; bonding a glass substrate to the strained silicon layer to form a composite wafer; splitting the composite wafer to provide a split wafer; and processing the split wafer to prepare it for subsequent device fabrication.

Abstract: A method of fabricating a low defect germanium thin film includes preparing a silicon wafer for germanium deposition; forming a germanium film using a two-step CVD process, annealing the germanium thin film using a multiple cycle process; implanting hydrogen ions; depositing and smoothing a layer of tetraethylorthosilicate oxide (TEOS); preparing a counter wafer; bonding the germanium thin film to a counter wafer to form a bonded structure; annealing the bonded structure at a temperature of at least 375° C. to facilitate splitting of the bonded wafer; splitting the bonded structure to expose the germanium thin film; removing any remaining silicon from the germanium thin film surface along with a portion of the germanium thin film defect zone; and incorporating the low-defect germanium thin film into the desired end-product device.

Abstract: A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.