Abstract: A method, system and computer program product for minimizing workload migrations during cloud maintenance operations. Upon receiving an indication that a scheduled maintenance operation is to be performed, a cloud controller uploads the maintenance binaries associated with the scheduled maintenance operation and analyzes the maintenance binaries so as to evaluate the requirements of the maintenance packages and dependencies associated with the scheduled maintenance operation. A matrix is then generated by the cloud controller to identify the classes of hardware that will be disrupted by the scheduled maintenance operation based on the analysis. The workloads running on the classes of hardware identified in the matrix will then be consolidated prior to the scheduled maintenance operation. By consolidating the workloads onto a fewer number of hardware components, a fewer number of workload migrations will need to be performed during the cloud maintenance operation.

Abstract: A method, system and computer program product for minimizing workload migrations during cloud maintenance operations. Upon receiving an indication that a scheduled maintenance operation is to be performed, a cloud controller uploads the maintenance binaries associated with the scheduled maintenance operation and analyzes the maintenance binaries so as to evaluate the requirements of the maintenance packages and dependencies associated with the scheduled maintenance operation. A matrix is then generated by the cloud controller to identify the classes of hardware that will be disrupted by the scheduled maintenance operation based on the analysis. The workloads running on the classes of hardware identified in the matrix will then be consolidated prior to the scheduled maintenance operation. By consolidating the workloads onto a fewer number of hardware components, a fewer number of workload migrations will need to be performed during the cloud maintenance operation.

Abstract: Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A method, system and computer program product for optimizing virtual machine deployment. A cloud controller pre-generates and stores a virtual machine's first-boot metadata (e.g., a RSA key) prior to the deployment of the virtual machine so that the virtual machine does not need to generate such metadata at deployment time thereby reducing the deployment time of the virtual machine. Instead, after the deployment and activation of the virtual machine, an activation agent running on the virtual machine requests the pre-generated first-boot metadata from the cloud controller. The cloud controller retrieves the requested pre-generated first-boot metadata to be transmitted to the requesting virtual machine and implements public-key cryptography so that the requesting virtual machine can verify the authenticity of the transmitted first-boot metadata. By reducing the deployment time for the virtual machine, cloud resources can be used for other activities.

Abstract: A method, system and computer program product for optimizing virtual machine deployment time. A cloud controller receives a request from a user to configure a virtual machine with a designated CPU capacity. If the designated CPU capacity is less than or equal to a threshold, then the cloud controller determines if there are additional cloud resources available to be allocated to deploy the virtual machine. If so, then the cloud controller allocates additional CPU capacity to the designated CPU capacity to be used to provision the virtual machine thereby enabling a multithreaded startup to initialize the operating system and middleware tiers so as to reduce the deployment time of the virtual machine. The additional resources would only be available during the initial deployment time of the virtual machine and removed before the user is granted access to the system when it comes online.

Abstract: A method, system and computer program product for optimizing storage system behavior in a cloud computing environment. An Input/Output (I/O) operation data is appended with a tag, where the tag indicates a class of data for the I/O operation data. Upon the storage controller reviewing the tag appended to the I/O operation data, the storage controller performs a table look-up for the storage policy associated with the determined class of data. The storage controller applies a map to determine a storage location for the I/O operation data in a drive device, where the map represents a logical volume which indicates a range of block data that is to be excluded for being stored on the drive device and a range of block data that is to be considered for being stored on the drive device. In this manner, granularity of storage policies is provided in a cloud computing environment.

Abstract: Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.

Abstract: A method, system and apparatus for selective macro event recording. In accordance with the present invention, events can be selectively included in a macro recording process, even where the events occur across different contexts such as different application windows in different applications. Specifically, once a macro recording session has been initiated for a particular application or application window, events occurring in different applications or application windows can be selected for inclusion in the macro through an append recording operation. Notably, the selective macro recording facility can be included as part of an operating environment, or as part of the individual applications executing within the operating environment.

Abstract: Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: Methods of providing a habitable community having usable habitation facilities, and electric and water utilities, including providing a community construction service pack and corresponding community construction services by which such service pack is rapidly installed at a location in need of such rapidly-built community. Such rapidly-built community may be used e.g. to meet the needs of a population suffering from a recent disaster and/or to meet the needs of a population in need of community facilities at a newly-to-be occupied site remote from human habitation and/or human habitation facilities. The invention thus is able to rapidly provide one or more limited-size functional communities on an urgent-need basis where each community initially has its own community local electric service system and its own community local water service, which may be functional even though local housing units may have been severely damaged or destroyed.

Abstract: Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.

Abstract: Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.