Abstract: An ATE calibration method and system that does not require external test equipment to calibrate individual functional pins and provides balanced timing skews among the functional pins and pincards is disclosed. A functional pin in the test system is selected as a reference or “golden” pin and another is selected as a precision measurement unit (PMU). External test equipment and the reference PMU are used to measure the AC and DC characteristics of the reference pin, and any deviation represents a measurement error in the reference PMU. All functional pins in the test system can be measured against the reference pin using the reference PMU, taking into account the measurement error, without the need for external test equipment. To ensure that skews are balanced among all pins, the location of the reference pin is selected to be as close as possible to the midpoint of the functional pin range.

Abstract: An ATE calibration method and system that does not require external test equipment to calibrate individual functional pins and provides balanced timing skews among the functional pins and pincards is disclosed. A functional pin in the test system is selected as a reference or “golden” pin and another is selected as a precision measurement unit (PMU). External test equipment and the reference PMU are used to measure the AC and DC characteristics of the reference pin, and any deviation represents a measurement error in the reference PMU. All functional pins in the test system can be measured against the reference pin using the reference PMU, taking into account the measurement error, without the need for external test equipment. To ensure that skews are balanced among all pins, the location of the reference pin is selected to be as close as possible to the midpoint of the functional pin range.

Abstract: One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

Abstract: One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

Abstract: A method to detect when a bus master device terminates a bus data transfer operation includes providing a first counter clocked by a first clock signal and providing a second counter clocked by a second clock signal. Outputs of the first and second counters are compared, and it is determined if termination of the bus transfer operation has occurred based on comparing the outputs.

Abstract: A Peripheral Component Interconnect (PCI) interface unit providing a duplicate set of control signals enhances the load bearing capacity of a PCI bus. The duplicate set of control signals permit devices coupled to the original set of control signals to be electrically decoupled from devices coupled to the duplicate set of control signals. Decoupling in this manner distributes PCI bus loads between a first sub-bus associated with the original set of control signals and a second sub-bus associated with the duplicate set of control signals; each sub-bus may support the maximum number of loads.

Abstract: A memory for storing address translation data includes one or more page table entry structures. Each page table entry structure includes a base address field to identify an allocated page of memory, a prior page field to identify zero or more allocated pages of memory that are sequential to and before that page of memory identified by the base address field, and a subsequent page field to identify zero or more allocated pages of memory that are sequential to and after that page identified by the base address field.

Abstract: A method to detect when a bus master device terminates a bus data transfer operation includes providing a first counter clocked by a first clock signal and providing a second counter clocked by a second clock signal. Outputs of the first and second counters are compared, and it is determined if termination of the bus transfer operation has occurred based on comparing the outputs.

Abstract: A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.

Abstract: A circuit to detect when an accelerated graphics port master device terminates a sideband bus data transfer operation The circuit includes a first register to cyclically generate a predetermined sequence of output signals at a rate determined by a first clock signal, a second register to cyclically generate the predetermined sequence of output signals at a rate determined by a second clock signal (each output signal of the second register having a corresponding first register output signal), and a detector to detect a mismatch between an output signal from the second register and a corresponding output signal from the first register.

Abstract: One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip containing a first bus arbitration circuit and a second bus arbitration circuit. A first set of grant lines originates from the first bus arbitration circuit and is used to grant control of a first bus to devices on the first bus. This first set of grant lines is divided into a first subset of grant lines and a second subset of grant lines. A second set of grant lines originates from the second bus arbitration circuit and is used to grant control of a second bus to devices on the second bus. This second set of grant lines is divided into a third subset of grant lines and a fourth subset of grant lines. A selector circuit selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines.

Abstract: One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins.

Abstract: A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.

Abstract: One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus arbitration circuit. A number of grant lines emanate from the bus arbitration circuit. An encoder circuit encodes the grant lines into a smaller number of encoded grant lines. A selector circuit selects outputs from between the encoded grant lines and a first subset of grant lines. These outputs pass through output pins off of the semiconductor chip. During a first mode of operation, the first subset of grant lines is driven through the plurality of output pins. During a second mode of operation, the encoded grant lines are driven through the output pins. A variation on the above embodiment includes a number of bus request lines, which are divided into a first subset and a second subset. The first subset of request lines feeds through a number of input pins into the bus arbitration circuit.

Abstract: One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating from a bus arbitration circuit and encoding the grant lines into a smaller number of encoded grant lines. The method selects outputs from between the encoded grant lines and a first subset of the grant lines. These outputs are driven off of a semiconductor chip through a number of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the output pins. During a second mode of operation, the encoded grant lines are selected to driven through the output pins. In a variation on the above embodiment, the method additionally receives a number of bus request lines. These request lines are divided into a first subset and a second subset. The first subset of request lines is received through a number of input pins from off of the semiconductor chip.

Abstract: A memory for storing address translation data includes one or more page table entry structures. Each page table entry structure includes a base address field to identify an allocated page of memory, a prior page field to identify zero or more allocated pages of memory that are sequential to and before that page of memory identified by the base address field, and a subsequent page field to identify zero or more allocated pages of memory that are sequential to and after that page identified by the base address field.

Abstract: A technique to arbitrate computer memory request signals includes selecting a first memory request signal (associated with a first requestor), associating an access count value with the first memory request signal, and allowing the first memory requestor to access the computer memory access count value consecutive times.

Abstract: An apparatus for leveling (136) a circuit board (105) against a rail (128, 130) of a part placement machine (102) comprises a plate (200) and at least one spring (404, 506, 507, 508). The circuit board (105) can have any one of a plurality of different predetermined thicknesses. The plate (200) is positioned beneath the rail (128, 130) and has first and second sides (204, 300). The first side (204) is dimensioned to support the circuit board (105). The plate (200) is moveable to a first predetermined distance from the rail (128, 130). The first predetermined distance is no smaller than a smallest one of the plurality of different predetermined thicknesses of the circuit board (105). The at least one spring (404, 506, 507, 508) is carried on the second side (300) of the plate (200) to bias the plate towards the rail (128, 130). The at least one spring (404, 506, 507, 508) is compressible to accommodate the circuit board (105) between the plate (200) and the rail (128, 130).

Abstract: A method and apparatus for determining if contention exists in a simulated electronic circuit due to multiple simulated drivers contending for the same simulated bus. A contention detection function counts the number of simulated drivers on the simulated bus which are active. If the number of active simulated drivers is greater than one, then an error message is generated reporting contention. The invention is suitable for computer implementation and is particularly well suited for simulation of an integrated circuit. A conversion function can be applied to translate the output of the simulated drivers into a format suitable for processing by the contention detection function and can also retranslate the output of the resolution function into a format suitable for further processing in the simulated electronic circuit. The active state of a simulated driver can be indicated by either a predetermined high voltage level or a predetermined low voltage level.

Abstract: A single queuing structure enqueues requests of multiple priorities. The queuing structure is especially well adapted for use with requests that are part of AGP operations. For instance, the queuing structure may enqueue low priority read/flush requests, high priority read/flush requests, low priority write requests, and high priority write requests. The queuing structure may be logically partitioned into logical sub-queues where each sub-queues is associated with requests of a given type and a given priority. Each of the logical sub-queues may be configured to operate in a first-in-first-out (FIFO) fashion. Separate pointers may be maintained for identifying the bottom of each of the logical sub-queues within the single queuing structure.