Abstract: In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.

Abstract: Human interferon-? protein analogs in which the asparagine at position 25, numbered in accordance with native human interferon-?, is recombinantly replaced with an aspartate residue exhibit a biological activity of human interferon-? (e.g. IFN-? 1b) at an increased level relative to IFN-? 1b. These analogs are obtained by introducing a gene coding for Asp25 IFN-? into a cell and expressing the recombinant protein. The resulting IFN-? protein analog is suitable for large scale manufacturing for incorporation in HA-containing or HA-free therapeutics for treatment of diseases including multiple sclerosis. A reduced Lys endoproteinase-C peptide map technique that produces a fingerprint profile for proteins using an enzymatic digest followed by RP-HPLC is also useful in quality control as an ID test for the IFN-? protein analog products.

Abstract: This invention relates to a bed including a frame with a substantially planar frame support surface. The bed also includes a width adjustment accessory with a mounting member and an extension member, the extension member providing a substantially planar extended support surface. The mounting member is configured to be attached relative to the frame so that the extended support surface is substantially planar with the frame support surface.

Abstract: In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.

Abstract: One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.

Abstract: One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.

Abstract: In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.

Abstract: In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.

Abstract: A method, system and apparatus for selective macro event recording. In accordance with the present invention, events can be selectively included in a macro recording process, even where the events occur across different contexts such as different application windows in different applications. Specifically, once a macro recording session has been initiated for a particular application or application window, events occurring in different applications or application windows can be selected for inclusion in the macro through an append recording operation. Notably, the selective macro recording facility can be included as part of an operating environment, or as part of the individual applications executing within the operating environment.

Abstract: In a memory hub system, several daisy-chained memory hubs are connected to a single memory controller. The memory hub transmitters and receivers operate in a high-speed clock domain, while the logic cores of the memory hubs operate in a low-speed clock domain. A clock domain interface advantageously provides data storage and transfer between the two clock domains without stalling the logic in the low-speed clock domain and without interrupting data movement in the high-speed clock domain.

Abstract: Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a thread to be used to communicate with an operating system and saving a context switch count, an offset, and a scale factor, received from the operating system, in the memory space.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.

Abstract: A filter system for receiving an oil-in-water emulsion contaminated with an emulsified contaminant oil, and separating the emulsified contaminant oil from the oil-in-water emulsion includes a filter media for receiving the oil-in-water emulsion and emulsified contaminant oil, having an inner filter element formed from a 95 percent single pass efficiency 48 micron (5 micron nominal) filtering material of needle punch polypropylene felt, an outer filter element formed from a 95 percent single pass efficiency 19 micron absolute filtering material of a polypropylene microfiber material and a porous spunbond polypropylene sandwiching the outer filter media. The filter element de-emulsifies the emulsified contaminant oil from the oil-in-water emulsion into the contaminant oil and the oil-in-water emulsion, separates the de-emulsified contaminant oil from the oil-in-water emulsion, coalesces the separated contaminant oil and passes both the coalesced de-emulsified contaminant oil and the oil-in-water emulsion.

Abstract: A filter system for receiving an oil-in-water emulsion contaminated with an emulsified contaminant oil, and separating the emulsified contaminant oil from the oil-in-water emulsion includes a filter media for receiving the oil-in-water emulsion and emulsified contaminant oil, having an inner filter element formed from a 95 percent single pass efficiency 48 micron (5 micron nominal) filtering material of needle punch polypropylene felt, an outer filter element formed from a 95 percent single pass efficiency 19 micron absolute filtering material of a polypropylene microfiber material and a porous spunbond polypropylene sandwiching the outer filter media. The filter clement de-emulsifies the emulsified contaminant oil from the oil-in-water emulsion into the contaminant oil and the oil-in-water emulsion, separates the de-emulsified contaminant oil from the oil-in-water emulsion, coalesces the separated contaminant oil and passes both the coalesced de-emulsified contaminant oil and the oil-in-water emulsion.