Patents by Inventor Duane R. Mills
Duane R. Mills has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868220Abstract: Methods, systems, and devices for efficient power scheme for redundancy are described. A memory device may include circuitry that stores memory address information related to one or more defective or unreliable memory components and that compares memory address information to memory addresses targeted for memory access operations. The memory device may selectively distribute a targeted memory address to one or more circuits within the circuitry based on whether those circuits store memory address information. Additionally or alternatively, the memory device may selectively power one or more circuits within the circuitry based on whether those circuits store memory address information.Type: GrantFiled: June 19, 2019Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Richard E. Fackenthal, Duane R. Mills
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Publication number: 20230422471Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.Type: ApplicationFiled: September 8, 2023Publication date: December 28, 2023Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
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Patent number: 11778806Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.Type: GrantFiled: July 29, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
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Publication number: 20230298652Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage struType: ApplicationFiled: May 23, 2023Publication date: September 21, 2023Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E. Fackenthal, Duane R. Mills
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Patent number: 11747982Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.Type: GrantFiled: September 29, 2021Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Duane R. Mills, Richard E. Fackenthal
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Patent number: 11688450Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage struType: GrantFiled: February 26, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E Fackenthal, Duane R. Mills
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Patent number: 11605412Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.Type: GrantFiled: March 9, 2021Date of Patent: March 14, 2023Assignee: Micron Technology, Inc.Inventors: Richard E. Fackenthal, Daniele Vimercati, Duane R. Mills
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Publication number: 20230031904Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
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Patent number: 11562805Abstract: Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.Type: GrantFiled: November 13, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Richard E. Fackenthal, Jahanshir Javanifard, Duane R. Mills
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Publication number: 20220278112Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage struType: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E. Fackenthal, Duane R. Mills
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Publication number: 20220019349Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventors: Duane R. Mills, Richard E. Fackenthal
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Patent number: 11222668Abstract: Methods, systems, and devices for memory cell sensing stress mitigation are described. A memory device may be configured to bias a memory cell to a voltage with a first polarity or a second polarity (e.g., a positive voltage or a negative voltage) during an access operation to level wear experienced by the memory cell during the access operation. For example, during a first read operation, a first pulse with the first polarity (e.g., a negative voltage) may be applied to the memory cell to read out a first logic state stored at the memory cell. During a second read operation, a second pulse with the second polarity (e.g., a positive voltage) may be applied to the memory cell to read out a second logic state stored at the memory cell. The memory device may include a selection component for selecting between the different pulses used for different read operations.Type: GrantFiled: August 27, 2020Date of Patent: January 11, 2022Assignee: Micron Technology, Inc.Inventors: Daniele Vimercati, Duane R. Mills, Richard E. Fackenthal, Yasuko Hattori
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Patent number: 11157176Abstract: Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.Type: GrantFiled: May 22, 2019Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventors: Duane R. Mills, Richard E. Fackenthal
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Publication number: 20210264960Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.Type: ApplicationFiled: March 9, 2021Publication date: August 26, 2021Inventors: Richard E. Fackenthal, Daniele Vimercati, Duane R. Mills
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Patent number: 11003361Abstract: In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear leveled.Type: GrantFiled: January 27, 2020Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventors: Richard E. Fackenthal, Duane R. Mills
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Publication number: 20210134386Abstract: Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.Type: ApplicationFiled: November 13, 2020Publication date: May 6, 2021Inventors: Richard E. Fackenthal, Jahanshir Javanifard, Duane R. Mills
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Patent number: 10971203Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.Type: GrantFiled: July 8, 2019Date of Patent: April 6, 2021Assignee: Micron Technology, Inc.Inventors: Richard E. Fackenthal, Daniele Vimercati, Duane R. Mills
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Publication number: 20200402606Abstract: Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Inventors: Richard E. Fackenthal, Jahanshir Javanifard, Duane R. Mills
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Publication number: 20200401490Abstract: Methods, systems, and devices for efficient power scheme for redundancy are described. A memory device may include circuitry that stores memory address information related to one or more defective or unreliable memory components and that compares memory address information to memory addresses targeted for memory access operations. The memory device may selectively distribute a targeted memory address to one or more circuits within the circuitry based on whether those circuits store memory address information. Additionally or alternatively, the memory device may selectively power one or more circuits within the circuitry based on whether those circuits store memory address information.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Inventors: Richard E. Fackenthal, Duane R. Mills
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Patent number: 10872678Abstract: Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.Type: GrantFiled: June 19, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Richard E. Fackenthal, Jahanshir Javanifard, Duane R. Mills