Abstract: A device with an in package power supply may be utilized to supply power to other components. As a result, the overall system size may be reduced and economies may be achieved.

Abstract: A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

Abstract: A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

Abstract: A memory system having memory cells for storing one of a plurality of threshold levels to store more than a single bit per cell is disclosed. The memory system contains a switch control to permit selection of an operating mode including a multi-level cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multi-level cell mode. A program circuit programs a single bit of data per memory cell for addressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multi-level cell mode.

Abstract: A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip.

Abstract: A powerdown controller receives a powerdown signal and causes a powerdown if the powerdown signal indicates a powerdown condition. An override signal also forces the powerdown controller to cause the powerdown when the powerdown signal is not indicating the powerdown condition. An override circuit generates the override signal if the powerdown condition is desired and the powerdown signal is not indicating the powerdown condition.

Abstract: An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address.

Abstract: A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.

Abstract: A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.

Abstract: Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

Abstract: An Address Transition Detection (ATD) circuit for use in memory devices. The ATD circuit includes a pulse generator for generating an ATD pulse. For asynchronous memory device, the pulse generator generates the ATD pulse in response to an address transition, wherein for synchronous devices, the pulse generator generates the ATD pulse in response to control signals that indicate a valid address. The ATD circuit also includes a control circuit and a mask circuit. The control circuit is operative to asserting a first control signal in response to receiving the pulse. The mask circuit is coupled between the output of the pulse generator and the control circuit for preventing propagation of the ATD pulse if the first control signal is active.

Abstract: A nonvolatile memory and a method for controlling the nonvolatile memory to switch between first and second data widths are described. The nonvolatile memory includes a first memory array, a second memory array, a first plurality of data pads, and a second plurality of data pads. A data width control circuit selectively couples the first and second plurality of data pads to the first and second memory arrays. A data width configuration cell is provided for configuring data width of the nonvolatile memory. A data width select circuit controls the data width control circuit to selectively couple the first and second plurality of data pads to the first and second memory arrays under the control of the data width configuration cell. When the data width configuration cell is in a first state, the first and second memory arrays are coupled to the first and second plurality of data pads such that the nonvolatile memory has a first data width.

Abstract: Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has first and second master latches to receive and store an external address. A first slave latch is also included to receive and store the external address from the first master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the second master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

Abstract: A nonvolatile memory device is described. The memory device includes a main memory array for storing data. The main memory array comprises a first block and a second block. A redundant memory array comprises a first redundant block and a second redundant block. The first redundant block comprises a first redundant column of memory cells and a second redundant column of memory cells. The second redundant block comprises a third redundant column of memory cells and a fourth redundant column of memory cells. A content addressable memory (CAM) comprises a first set of CAM cells for storing a first address of a first defective column in the main memory array and a second set of CAM cells for storing a second address of a second defective column in the main memory array. The first set of CAM cells cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block.

Abstract: A memory device is described. The memory device includes a memory array. A configuration cell configures the memory device with respect to memory device operation. The configuration cell is coupled to various internal circuits of the memory device. The configuration cell is initially in a first state and can selectably be placed into a second state. Once the configuration cell is placed into the second state, the configuration cell is impeded from returning to the first state. A status cell is initially in a third state and can selectably be placed into a fourth state. Once the status cell is placed into the fourth state, the status cell is impeded from returning to the third state. A control circuit is coupled between the status cell and the configuration cell. If the memory device is in a standby mode, and the status cell is in the third state, then the control circuit turns off the current of the configuration cell. A method of testing a memory device is also described.