Abstract: Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

Abstract: Examples described herein relate to a network interface. In some examples, the network interface is to access data designated for transmission in at least one packet to multiple memory nodes by inclusion of an multicast identifier of a memory node group and transmit the at least one packet to a destination network device, wherein the multicast identifier of the memory node group in the at least one packet is to cause an intermediate network device to multicast the packet to multiple memory nodes. In some examples, a memory node comprises a memory pool that includes one or more of: volatile memory, non-volatile memory, or persistent memory. In some examples, the intermediate network device comprises a switch configured to determine network addresses of memory nodes associated with the multicast identifier of the memory node group.

Abstract: Examples herein relate to a system capable of coupling to a remote memory pool, the system comprising: a memory controller and an interface to a connection, the interface coupled to the memory controller. In some examples, the interface is to translate a format of a memory access request to a format accepted by the memory controller and the memory controller is to provide the translated memory access request in a format accepted by a media. In some examples, a controller is to measure a number of addressable regions that are least accessed and cause at least one of the least accessed regions to be evicted to a local or remote memory device with relatively higher latency.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to provide an interface to a pooled memory that is configured as a combination of local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, allocate respective memory portions of the pooled memory to respective tenants, associate respective memory balloons with the respective tenants that correspond to the allocated respective memory portions, and manage the respective memory balloons based on the respective tenants and two or more memory tiers associated with the pooled memory. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

Abstract: A function as a service (FAAS) computing system includes processing to adaptively select function flavors to implement requested functions. Processing includes receiving a request to perform a function from an application, discovering one or more flavors for the function, each flavor to implement the function on computing hardware components of computing platforms, and selecting a first function flavor to implement the requested function. Processing further includes causing execution of the first function flavor by a first computing hardware component for the requested function, determining whether performance degradation of the first computing hardware component exists for the first function flavor, and if so, selecting a second function flavor to implement the requested function, and causing execution of the second function flavor by a second computing hardware component for the requested function, and if not, continuing to cause execution of the first function flavor for requests for the function.

Abstract: Context aware backlighting techniques include determining a focal point of a display space based on a user display context. The user display context represents an area of interest on the monitor. The user display context can be based on eye tracking data, ambient light data, motion sensing data, cursor location in the display space, an image content, proximity data, or the like and any combination thereof. A first set of one or more of a plurality of backlight sections corresponding to the determined focal point of the display space can be driven to output at a first intensity level, while a second set of one or more of the plurality of backlight sections can be driven to output at a second intensity level.

Abstract: Context aware backlighting techniques include determining a focal point of a display space based on a user display context. The user display context represents an area of interest on the monitor. The user display context can be based on eye tracking data, ambient light data, motion sensing data, cursor location in the display space, an image content, proximity data, or the like and any combination thereof. A first set of one or more of a plurality of backlight sections corresponding to the determined focal point of the display space can be driven to output at a first intensity level, while a second set of one or more of the plurality of backlight sections can be driven to output at a second intensity level.

Abstract: Context aware backlighting techniques include determining a focal point of a display space based on a user display context. The user display context represents an area of interest on the monitor. The user display context can be based on eye tracking data, ambient light data, motion sensing data, cursor location in the display space, an image content, proximity data, or the like and any combination thereof. A first set of one or more of a plurality of backlight sections corresponding to the determined focal point of the display space can be driven to output at a first intensity level, while a second set of one or more of the plurality of backlight sections can be driven to output at a second intensity level.

Abstract: Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

Abstract: Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

Abstract: A processor device has a cache, and a cache controller that manages the replacement of a number of cache lines in the cache, in accordance with a replacement policy. A storage location is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region. Upon a cache miss of an address that lies in the real time region, the cache controller responds by loading content at the address into a cache line, and then prevents the cache line from aging as would a cache line that is in the cacheable region. Other embodiments are also described and claimed.

Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Abstract: A RDIMM enabled memory controller may support a UDIMM by way of a register chip and a PLL chip being implemented in operational relationship with a memory slot and a memory controller configured to support a RDIMM. The memory controller may drive address and control signals from the memory controller to the register chip, and the address and control signals may be provided from the register chip to the memory slot after one clock cycle, in response to the register chip latching onto the address and control signals from the memory controller on a rising clock edge.

Abstract: A configuration system is described. In an implementation, a method includes determining through execution of a configuration system whether an application qualifies as a member of one or more of a plurality of groups. Each of the groups defines one or more criteria for membership and has at least one corresponding block having configuration data. The determining is performed based on whether the application satisfies the one or more criteria. For each of the groups, of which, the application qualifies as a member, the configuration data of the at least one corresponding block is loaded.

Abstract: In one embodiment, the present invention includes a counter to count core clocks, where the counter has a value to be incremented from zero to one less than a first bus ratio. Coupled to the counter may be a control logic to generate a control signal to change from the first bus ratio to a second bus ratio, where the control logic is coupled to receive the counter value and control the counter based on this value. In this way, the bus ratio can change without draining the transaction queues of a processor. Other embodiments are described and claimed.

Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.

Abstract: An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.