Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.

Abstract: In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed.

Abstract: A RDIMM enabled memory controller may support a UDIMM by way of a register chip and a PLL chip being implemented in operational relationship with a memory slot and a memory controller configured to support a RDIMM. The memory controller may drive address and control signals from the memory controller to the register chip, and the address and control signals may be provided from the register chip to the memory slot after one clock cycle, in response to the register chip latching onto the address and control signals from the memory controller on a rising clock edge.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: Automatically determining the conformance of database server schema. Maintaining conformance of database schema helps manage and sustain database driven services and applications. Schema for a pair of randomly selected databases are generated and compared. A diffgram is generated from the difference of the database schema. An alarm message can then be sent to an alarm server with the differences of the comparable databases. A master schema dump can be compared to selected database servers within the database system concurrently with the comparable database pair schema processing. A diffgram is generated in response to the comparison between the selected database schema and the master schema.

Abstract: Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: Systems and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Various techniques are provided for detecting a defect in a portion of memory and dynamically avoiding future attempts to access the defective portion of memory. More specifically, the techniques detect and avoid both hard and erratic errors.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Abstract: Automatically determining the conformance of database server schema. Maintaining conformance of database schema helps manage and sustain database driven services and applications. Schema for a pair of randomly selected databases are generated and compared. A diffgram is generated from the difference of the database schema. An alarm message can then be sent to an alarm server with the differences of the comparable databases. A master schema dump can be compared to selected database servers within the database system concurrently with the comparable database pair schema processing. A diffgram is generated in response to the comparison between the selected database schema and the master schema.

Abstract: The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.